Merge tag 'mmc-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Broadcom BCM2835 SDHOST controller

This file documents differences between the core properties described

by mmc.txt and the properties that represent the BCM2835 controller.

Required properties:

- compatible: Should be "brcm,bcm2835-sdhost".

- clocks: The clock feeding the SDHOST controller.

Optional properties:

- dmas: DMA channel for read and write.

          See Documentation/devicetree/bindings/dma/dma.txt for details

Example:

sdhost: mmc@7e202000 {

	compatible = "brcm,bcm2835-sdhost";

	reg = <0x7e202000 0x100>;

	interrupts = <2 24>;

	clocks = <&clocks BCM2835_CLOCK_VPU>;

	dmas = <&dma 13>;

	dma-names = "rx-tx";

};

* Cavium Octeon & ThunderX MMC controller

The highspeed MMC host controller on Caviums SoCs provides an interface

for MMC and SD types of memory cards.

Supported maximum speeds are the ones of the eMMC standard 4.41 as well

as the speed of SD standard 4.0. Only 3.3 Volt is supported.

Required properties:

 - compatible : should be one of:

   cavium,octeon-6130-mmc

   cavium,octeon-7890-mmc

   cavium,thunder-8190-mmc

   cavium,thunder-8390-mmc

   mmc-slot

 - reg : mmc controller base registers

 - clocks : phandle

Optional properties:

 - for cd, bus-width and additional generic mmc parameters

   please refer to mmc.txt within this directory

 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command

 - cavium,dat-clk-skew : number of coprocessor clocks before sampling data

Deprecated properties:

- spi-max-frequency : use max-frequency instead

- cavium,bus-max-width : use bus-width instead

- power-gpios : use vmmc-supply instead

- cavium,octeon-6130-mmc-slot : use mmc-slot instead

Examples:

	mmc_1_4: mmc@1,4 {

		compatible = "cavium,thunder-8390-mmc";

		reg = <0x0c00 0 0 0 0>;	/* DEVFN = 0x0c (1:4) */

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&sclk>;

		mmc-slot@0 {

			compatible = "mmc-slot";

			reg = <0>;

			vmmc-supply = <&mmc_supply_3v3>;

			max-frequency = <42000000>;

			bus-width = <4>;

			cap-sd-highspeed;

		};

		mmc-slot@1 {

			compatible = "mmc-slot";

			reg = <1>;

			vmmc-supply = <&mmc_supply_3v3>;

			max-frequency = <42000000>;

			bus-width = <8>;

			cap-mmc-highspeed;

			non-removable;

		};

	};

Marvell Xenon SDHCI Controller device tree bindings

This file documents differences between the core mmc properties

described by mmc.txt and the properties used by the Xenon implementation.

Multiple SDHCs might be put into a single Xenon IP, to save size and cost.

Each SDHC is independent and owns independent resources, such as register sets,

clock and PHY.

Each SDHC should have an independent device tree node.

Required Properties:

- compatible: should be one of the following

  - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.

  Must provide a second register area and marvell,pad-type.

  - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.

  - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.

- clocks:

  Array of clocks required for SDHC.

  Require at least input clock for Xenon IP core.

- clock-names:

  Array of names corresponding to clocks property.

  The input clock for Xenon IP core should be named as "core".

- reg:

  * For "marvell,armada-3700-sdhci", two register areas.

    The first one for Xenon IP register. The second one for the Armada 3700 SoC

    PHY PAD Voltage Control register.

    Please follow the examples with compatible "marvell,armada-3700-sdhci"

    in below.

    Please also check property marvell,pad-type in below.

  * For other compatible strings, one register area for Xenon IP.

Optional Properties:

- marvell,xenon-sdhc-id:

  Indicate the corresponding bit index of current SDHC in

  SDHC System Operation Control Register Bit[7:0].

  Set/clear the corresponding bit to enable/disable current SDHC.

  If Xenon IP contains only one SDHC, this property is optional.

- marvell,xenon-phy-type:

  Xenon support multiple types of PHYs.

  To select eMMC 5.1 PHY, set:

  marvell,xenon-phy-type = "emmc 5.1 phy"

  eMMC 5.1 PHY is the default choice if this property is not provided.

  To select eMMC 5.0 PHY, set:

  marvell,xenon-phy-type = "emmc 5.0 phy"

  All those types of PHYs can support eMMC, SD and SDIO.

  Please note that this property only presents the type of PHY.

  It doesn't stand for the entire SDHC type or property.

  For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only

  supports eMMC 5.1.

- marvell,xenon-phy-znr:

  Set PHY ZNR value.

  Only available for eMMC PHY.

  Valid range = [0:0x1F].

  ZNR is set as 0xF by default if this property is not provided.

- marvell,xenon-phy-zpr:

  Set PHY ZPR value.

  Only available for eMMC PHY.

  Valid range = [0:0x1F].

  ZPR is set as 0xF by default if this property is not provided.

- marvell,xenon-phy-nr-success-tun:

  Set the number of required consecutive successful sampling points

  used to identify a valid sampling window, in tuning process.

  Valid range = [1:7].

  Set as 0x4 by default if this property is not provided.

- marvell,xenon-phy-tun-step-divider:

  Set the divider for calculating TUN_STEP.

  Set as 64 by default if this property is not provided.

- marvell,xenon-phy-slow-mode:

  If this property is selected, transfers will bypass PHY.

  Only available when bus frequency lower than 55MHz in SDR mode.

  Disabled by default. Please only try this property if timing issues

  always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,

  SD Default Speed and HS mode and eMMC legacy speed mode.

- marvell,xenon-tun-count:

  Xenon SDHC SoC usually doesn't provide re-tuning counter in

  Capabilities Register 3 Bit[11:8].

  This property provides the re-tuning counter.

  If this property is not set, default re-tuning counter will

  be set as 0x9 in driver.

- marvell,pad-type:

  Type of Armada 3700 SoC PHY PAD Voltage Controller register.

  Only valid when "marvell,armada-3700-sdhci" is selected.

  Two types: "sd" and "fixed-1-8v".

  If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is

  switched to 1.8V when later in higher speed mode.

  If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.

  Please follow the examples with compatible "marvell,armada-3700-sdhci"

  in below.

Example:

- For eMMC:

	sdhci@aa0000 {

		compatible = "marvell,armada-ap806-sdhci";

		reg = <0xaa0000 0x1000>;

		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>

		clocks = <&emmc_clk>;

		clock-names = "core";

		bus-width = <4>;

		marvell,xenon-phy-slow-mode;

		marvell,xenon-tun-count = <11>;

		non-removable;

		no-sd;

		no-sdio;

		/* Vmmc and Vqmmc are both fixed */

	};

- For SD/SDIO:

	sdhci@ab0000 {

		compatible = "marvell,armada-cp110-sdhci";

		reg = <0xab0000 0x1000>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>

		vqmmc-supply = <&sd_vqmmc_regulator>;

		vmmc-supply = <&sd_vmmc_regulator>;

		clocks = <&sdclk>;

		clock-names = "core";

		bus-width = <4>;

		marvell,xenon-tun-count = <9>;

	};

- For eMMC with compatible "marvell,armada-3700-sdhci":

	sdhci@aa0000 {

		compatible = "marvell,armada-3700-sdhci";

		reg = <0xaa0000 0x1000>,

		      <phy_addr 0x4>;

		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>

		clocks = <&emmcclk>;

		clock-names = "core";

		bus-width = <8>;

		mmc-ddr-1_8v;

		mmc-hs400-1_8v;

		non-removable;

		no-sd;

		no-sdio;

		/* Vmmc and Vqmmc are both fixed */

		marvell,pad-type = "fixed-1-8v";

	};

- For SD/SDIO with compatible "marvell,armada-3700-sdhci":

	sdhci@ab0000 {

		compatible = "marvell,armada-3700-sdhci";

		reg = <0xab0000 0x1000>,

		      <phy_addr 0x4>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>

		vqmmc-supply = <&sd_regulator>;

		/* Vmmc is fixed */

		clocks = <&sdclk>;

		clock-names = "core";

		bus-width = <4>;

		marvell,pad-type = "sd";

	};

- assigned-clocks: PLL of the source clock

- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock

- hs400-ds-delay: HS400 DS delay setting

- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.

				This field has total 32 stages.

				The value is an integer from 0 to 31.

- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting

				This field has total 32 stages.

				The value is an integer from 0 to 31.

- mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection

				       If present,HS400 command responses are sampled on rising edges.

				       If not present,HS400 command responses are sampled on falling edges.

Examples:

mmc0: mmc@11230000 {

	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;

	hs400-ds-delay = <0x14015>;

	mediatek,hs200-cmd-int-delay = <26>;

	mediatek,hs400-cmd-int-delay = <14>;

	mediatek,hs400-cmd-resp-sel-rising;

};

by mmc.txt and the properties used by the sdhci-tegra driver.

Required properties:

- compatible : For Tegra20, must contain "nvidia,tegra20-sdhci".

  For Tegra30, must contain "nvidia,tegra30-sdhci".  For Tegra114,

  must contain "nvidia,tegra114-sdhci".  For Tegra124, must contain

  "nvidia,tegra124-sdhci".  Otherwise, must contain "nvidia,<chip>-sdhci",

  plus one of the above, where <chip> is tegra132 or tegra210.

- compatible : should be one of:

  - "nvidia,tegra20-sdhci": for Tegra20

  - "nvidia,tegra30-sdhci": for Tegra30

  - "nvidia,tegra114-sdhci": for Tegra114

  - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132

  - "nvidia,tegra210-sdhci": for Tegra210

  - "nvidia,tegra186-sdhci": for Tegra186

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.

- resets : Must contain an entry for each entry in reset-names.