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Commit be338e4c authored Jan 31, 2016 by Vishnu Patekar Committed by Maxime Ripard Feb 02, 2016

clk: sunxi: add bus gates for A83T



A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent 2d6f5f0c

Documentation/devicetree/bindings/clock/sunxi.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -58,6 +58,7 @@ Required properties:
		"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
		"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
		"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
		"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
		"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
		"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
		"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10

drivers/clk/sunxi/clk-sun8i-bus-gates.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -109,3 +109,5 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)

		CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
		sun8i_h3_bus_gates_init);
		CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
		sun8i_h3_bus_gates_init);