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Commit bd1b5f58 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.17-next-dts64' of... 

Merge tag 'v4.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

- add clock and pinctrl nodes for mt2712e
- add High-Speed DMA and audio nodes for mt7622

* tag 'v4.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux

:
  arm64: dts: mt7622: add audio related device nodes
  arm64: dts: mt7622: add High-Speed DMA device nodes
  arm64: dts: mt2712: add pintcrl device node.
  arm64: dts: mt2712: add pintcrl file
  arm64: dts: add clock device nodes of MT2712

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 5e377141 f1e0d0d8

arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h

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+1123 −0

File added.

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arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+46 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/mt2712-power.h>

#include "mt2712-pinfunc.h"



/ {

	compatible = "mediatek,mt2712";
@@ -199,6 +200,34 @@ 
		clock-output-names = "clkaud_ext_i_2";

	};



	clki2si0_mck_i: oscillator@6 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

		clock-output-names = "clki2si0_mck_i";

	};



	clki2si1_mck_i: oscillator@7 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

		clock-output-names = "clki2si1_mck_i";

	};



	clki2si2_mck_i: oscillator@8 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

		clock-output-names = "clki2si2_mck_i";

	};



	clktdmin_mclk_i: oscillator@9 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <30000000>;

		clock-output-names = "clktdmin_mclk_i";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;
@@ -230,6 +259,23 @@ 
		#clock-cells = <1>;

	};



	syscfg_pctl_a: syscfg_pctl_a@10005000 {

		compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";

		reg = <0 0x10005000 0 0x1000>;

	};



	pio: pinctrl@10005000 {

		compatible = "mediatek,mt2712-pinctrl";

		reg = <0 0x1000b000 0 0x1000>;

		mediatek,pctl-regmap = <&syscfg_pctl_a>;

		pins-are-numbered;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

	};



	scpsys: scpsys@10006000 {

		compatible = "mediatek,mt2712-scpsys", "syscon";

		#power-domain-cells = <1>;

arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

+9 −2
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";



	chosen {

		bootargs = "console=ttyS0,115200n1";

		bootargs = "console=ttyS0,115200n1 swiotlb=512";

	};



	cpus {
@@ -163,10 +163,17 @@ 
	i2s1_pins: i2s1-pins {

		mux {

			function = "i2s";

			groups =  "i2s_out_bclk_ws_mclk",

			groups =  "i2s_out_mclk_bclk_ws",

				  "i2s1_in_data",

				  "i2s1_out_data";

		};



		conf {

			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",

			       "I2S_WS", "I2S_MCLK";

			drive-strength = <12>;

			bias-pull-down;

		};

	};



	irrx_pins: irrx-pins {

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+99 −0
Original line number Diff line number Diff line
@@ -527,6 +527,95 @@ 
		status = "disabled";

	};



	audsys: clock-controller@11220000 {

		compatible = "mediatek,mt7622-audsys", "syscon";

		reg = <0 0x11220000 0 0x2000>;

		#clock-cells = <1>;



		afe: audio-controller {

			compatible = "mediatek,mt7622-audio";

			interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,

				      <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;

			interrupt-names	= "afe", "asys";



			clocks = <&infracfg CLK_INFRA_AUDIO_PD>,

				 <&topckgen CLK_TOP_AUD1_SEL>,

				 <&topckgen CLK_TOP_AUD2_SEL>,

				 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,

				 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,

				 <&topckgen CLK_TOP_I2S0_MCK_SEL>,

				 <&topckgen CLK_TOP_I2S1_MCK_SEL>,

				 <&topckgen CLK_TOP_I2S2_MCK_SEL>,

				 <&topckgen CLK_TOP_I2S3_MCK_SEL>,

				 <&topckgen CLK_TOP_I2S0_MCK_DIV>,

				 <&topckgen CLK_TOP_I2S1_MCK_DIV>,

				 <&topckgen CLK_TOP_I2S2_MCK_DIV>,

				 <&topckgen CLK_TOP_I2S3_MCK_DIV>,

				 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,

				 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,

				 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,

				 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,

				 <&audsys CLK_AUDIO_I2SO1>,

				 <&audsys CLK_AUDIO_I2SO2>,

				 <&audsys CLK_AUDIO_I2SO3>,

				 <&audsys CLK_AUDIO_I2SO4>,

				 <&audsys CLK_AUDIO_I2SIN1>,

				 <&audsys CLK_AUDIO_I2SIN2>,

				 <&audsys CLK_AUDIO_I2SIN3>,

				 <&audsys CLK_AUDIO_I2SIN4>,

				 <&audsys CLK_AUDIO_ASRCO1>,

				 <&audsys CLK_AUDIO_ASRCO2>,

				 <&audsys CLK_AUDIO_ASRCO3>,

				 <&audsys CLK_AUDIO_ASRCO4>,

				 <&audsys CLK_AUDIO_AFE>,

				 <&audsys CLK_AUDIO_AFE_CONN>,

				 <&audsys CLK_AUDIO_A1SYS>,

				 <&audsys CLK_AUDIO_A2SYS>;



			clock-names = "infra_sys_audio_clk",

				      "top_audio_mux1_sel",

				      "top_audio_mux2_sel",

				      "top_audio_a1sys_hp",

				      "top_audio_a2sys_hp",

				      "i2s0_src_sel",

				      "i2s1_src_sel",

				      "i2s2_src_sel",

				      "i2s3_src_sel",

				      "i2s0_src_div",

				      "i2s1_src_div",

				      "i2s2_src_div",

				      "i2s3_src_div",

				      "i2s0_mclk_en",

				      "i2s1_mclk_en",

				      "i2s2_mclk_en",

				      "i2s3_mclk_en",

				      "i2so0_hop_ck",

				      "i2so1_hop_ck",

				      "i2so2_hop_ck",

				      "i2so3_hop_ck",

				      "i2si0_hop_ck",

				      "i2si1_hop_ck",

				      "i2si2_hop_ck",

				      "i2si3_hop_ck",

				      "asrc0_out_ck",

				      "asrc1_out_ck",

				      "asrc2_out_ck",

				      "asrc3_out_ck",

				      "audio_afe_pd",

				      "audio_afe_conn_pd",

				      "audio_a1sys_pd",

				      "audio_a2sys_pd";



			assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,

					  <&topckgen CLK_TOP_A2SYS_HP_SEL>,

					  <&topckgen CLK_TOP_A1SYS_HP_DIV>,

					  <&topckgen CLK_TOP_A2SYS_HP_DIV>;

			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,

						 <&topckgen CLK_TOP_AUD2PLL>;

			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;

		};

	};



	mmc0: mmc@11230000 {

		compatible = "mediatek,mt7622-mmc";

		reg = <0 0x11230000 0 0x1000>;
@@ -735,6 +824,16 @@ 
		#reset-cells = <1>;

	};



	hsdma: dma-controller@1b007000 {

		compatible = "mediatek,mt7622-hsdma";

		reg = <0 0x1b007000 0 0x1000>;

		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&ethsys CLK_ETH_HSDMA_EN>;

		clock-names = "hsdma";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;

		#dma-cells = <1>;

	};



	eth: ethernet@1b100000 {

		compatible = "mediatek,mt7622-eth",

			     "mediatek,mt2701-eth",