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Commit 5e377141 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.17-next-dts32' of... 

Merge tag 'v4.17-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

convert to SPDX IDs

mt7623:
- add audio, bluetooth, highspees DMA and SPI-NOR nodes
- fix invalid memory nodes by not using skeleton64.dtsi
- fix memory size for bananapi-r2
- fix dtc warnings
- refactor dts and dtsi to aviod code duplication
- add mt7623n and mt7623a reference boards

* tag 'v4.17-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux

:
  arm: dts: mt7623: add MT7623N reference board with eMMC
  arm: dts: mt7623: add MT7623A reference boards
  arm: dts: mt7623: add MT7623A SoC level DTS
  arm: dts: mt7623: extend common file reused by all boards with MT7623 SoCs
  arm: dts: mt6323: move node mt6323 leds to mt6323.dtsi
  arm: dts: mt7623: add BTIF, HSDMA and SPI-NOR device nodes
  arm: dts: mt7623: fix all Warnings (unit_address_vs_reg)
  arm: dts: mt7623: fix available memory size on bananapi-r2
  arm: dts: mt7623: fix invalid memory node being generated
  arm: dts: mediatek: converted to using SPDX identifiers
  arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3112013b dd0dcf00

arch/arm/boot/dts/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -1150,6 +1150,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ 
	mt6580-evbp1.dtb \

	mt6589-aquaris5.dtb \

	mt6592-evb.dtb \

	mt7623a-rfb-emmc.dtb \

	mt7623a-rfb-nand.dtb \

	mt7623n-rfb-emmc.dtb \

	mt7623n-rfb-nand.dtb \

	mt7623n-bananapi-bpi-r2.dtb \

	mt8127-moose.dtb \

arch/arm/boot/dts/mt2701-evb.dts

+1 −8
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2015 MediaTek Inc.

 * Author: Erin Lo <erin.lo@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;

arch/arm/boot/dts/mt2701.dtsi

+91 −106
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2015 MediaTek Inc.

 * Author: Erin.Lo <erin.lo@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/clock/mt2701-clk.h>
@@ -426,10 +419,13 @@ 
		status = "disabled";

	};



	afe: audio-controller@11220000 {

	audsys: clock-controller@11220000 {

		compatible = "mediatek,mt2701-audsys", "syscon";

		reg = <0 0x11220000 0 0x2000>;

		#clock-cells = <1>;



		afe: audio-controller {

			compatible = "mediatek,mt2701-audio";

		reg = <0 0x11220000 0 0x2000>,

		      <0 0x112a0000 0 0x20000>;

			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,

				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;

			interrupt-names	= "afe", "asys";
@@ -438,92 +434,81 @@ 
			clocks = <&infracfg CLK_INFRA_AUDIO>,

				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,

				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,

			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,

			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,

				 <&topckgen CLK_TOP_AUD_48K_TIMING>,

				 <&topckgen CLK_TOP_AUD_44K_TIMING>,

			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,

			 <&topckgen CLK_TOP_APLL_SEL>,

			 <&topckgen CLK_TOP_AUD1PLL_98M>,

			 <&topckgen CLK_TOP_AUD2PLL_90M>,

			 <&topckgen CLK_TOP_HADDS2PLL_98M>,

			 <&topckgen CLK_TOP_HADDS2PLL_294M>,

			 <&topckgen CLK_TOP_AUDPLL>,

			 <&topckgen CLK_TOP_AUDPLL_D4>,

			 <&topckgen CLK_TOP_AUDPLL_D8>,

			 <&topckgen CLK_TOP_AUDPLL_D16>,

			 <&topckgen CLK_TOP_AUDPLL_D24>,

			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,

			 <&clk26m>,

			 <&topckgen CLK_TOP_SYSPLL1_D4>,

				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,

			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,

			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,

				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,

			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,

			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,

				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,

				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,

				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,

				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,

			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,

			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,

			 <&topckgen CLK_TOP_ASM_M_SEL>,

			 <&topckgen CLK_TOP_ASM_H_SEL>,

			 <&topckgen CLK_TOP_UNIVPLL2_D4>,

			 <&topckgen CLK_TOP_UNIVPLL2_D2>,

			 <&topckgen CLK_TOP_SYSPLL_D5>;

				 <&audsys CLK_AUD_I2SO1>,

				 <&audsys CLK_AUD_I2SO2>,

				 <&audsys CLK_AUD_I2SO3>,

				 <&audsys CLK_AUD_I2SO4>,

				 <&audsys CLK_AUD_I2SIN1>,

				 <&audsys CLK_AUD_I2SIN2>,

				 <&audsys CLK_AUD_I2SIN3>,

				 <&audsys CLK_AUD_I2SIN4>,

				 <&audsys CLK_AUD_ASRCO1>,

				 <&audsys CLK_AUD_ASRCO2>,

				 <&audsys CLK_AUD_ASRCO3>,

				 <&audsys CLK_AUD_ASRCO4>,

				 <&audsys CLK_AUD_AFE>,

				 <&audsys CLK_AUD_AFE_CONN>,

				 <&audsys CLK_AUD_A1SYS>,

				 <&audsys CLK_AUD_A2SYS>,

				 <&audsys CLK_AUD_AFE_MRGIF>;



			clock-names = "infra_sys_audio_clk",

				      "top_audio_mux1_sel",

				      "top_audio_mux2_sel",

			 "top_audio_mux1_div",

			 "top_audio_mux2_div",

			 "top_audio_48k_timing",

			 "top_audio_44k_timing",

			 "top_audpll_mux_sel",

			 "top_apll_sel",

			 "top_aud1_pll_98M",

			 "top_aud2_pll_90M",

			 "top_hadds2_pll_98M",

			 "top_hadds2_pll_294M",

			 "top_audpll",

			 "top_audpll_d4",

			 "top_audpll_d8",

			 "top_audpll_d16",

			 "top_audpll_d24",

			 "top_audintbus_sel",

			 "clk_26m",

			 "top_syspll1_d4",

			 "top_aud_k1_src_sel",

			 "top_aud_k2_src_sel",

			 "top_aud_k3_src_sel",

			 "top_aud_k4_src_sel",

			 "top_aud_k5_src_sel",

			 "top_aud_k6_src_sel",

			 "top_aud_k1_src_div",

			 "top_aud_k2_src_div",

			 "top_aud_k3_src_div",

			 "top_aud_k4_src_div",

			 "top_aud_k5_src_div",

			 "top_aud_k6_src_div",

			 "top_aud_i2s1_mclk",

			 "top_aud_i2s2_mclk",

			 "top_aud_i2s3_mclk",

			 "top_aud_i2s4_mclk",

			 "top_aud_i2s5_mclk",

			 "top_aud_i2s6_mclk",

			 "top_asm_m_sel",

			 "top_asm_h_sel",

			 "top_univpll2_d4",

			 "top_univpll2_d2",

			 "top_syspll_d5";

				      "top_audio_a1sys_hp",

				      "top_audio_a2sys_hp",

				      "i2s0_src_sel",

				      "i2s1_src_sel",

				      "i2s2_src_sel",

				      "i2s3_src_sel",

				      "i2s0_src_div",

				      "i2s1_src_div",

				      "i2s2_src_div",

				      "i2s3_src_div",

				      "i2s0_mclk_en",

				      "i2s1_mclk_en",

				      "i2s2_mclk_en",

				      "i2s3_mclk_en",

				      "i2so0_hop_ck",

				      "i2so1_hop_ck",

				      "i2so2_hop_ck",

				      "i2so3_hop_ck",

				      "i2si0_hop_ck",

				      "i2si1_hop_ck",

				      "i2si2_hop_ck",

				      "i2si3_hop_ck",

				      "asrc0_out_ck",

				      "asrc1_out_ck",

				      "asrc2_out_ck",

				      "asrc3_out_ck",

				      "audio_afe_pd",

				      "audio_afe_conn_pd",

				      "audio_a1sys_pd",

				      "audio_a2sys_pd",

				      "audio_mrgif_pd";



			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,

					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,

					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,

					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;

			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,

						 <&topckgen CLK_TOP_AUD2PLL_90M>;

			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;

		};

	};



	mmsys: syscon@14000000 {

arch/arm/boot/dts/mt6323.dtsi

+9 −8
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2017 MediaTek Inc.

 * Copyright (c) 2017-2018 MediaTek Inc.

 * Author: John Crispin <john@phrozen.org>

 *	   Sean Wang <sean.wang@mediatek.com>

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&pwrap {
@@ -20,6 +14,13 @@ 
		interrupt-controller;

		#interrupt-cells = <2>;



		mt6323_leds: leds {

			compatible = "mediatek,mt6323-led";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		mt6323regulator: mt6323regulator{

			compatible = "mediatek,mt6323-regulator";

arch/arm/boot/dts/mt6580-evbp1.dts

+1 −8
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2015 MediaTek Inc.

 * Author: Mars.C <mars.cheng@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;