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Commit b5fa57dd authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by Jani Nikula
Browse files

drm/i915/perf: fix flex eu registers programming 



We were reserving fewer dwords in the ring than necessary. Indeed
we're always writing all registers once, so discard the actual number
of registers given by the user and just program the whitelisted ones
once.

Fixes: 19f81df2 ("drm/i915/perf: Add OA unit support for Gen 8+")
Reported-by: default avatarMatthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: <stable@vger.kernel.org> # v4.12+
Link: https://patchwork.freedesktop.org/patch/msgid/20170803165812.2373-6-lionel.g.landwerlin@intel.com


(cherry picked from commit 01d928e9)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 5e2d0967

drivers/gpu/drm/i915/i915_perf.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -1601,11 +1601,11 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) 
	u32 *cs;

	u32 *cs;

	int i;

	int i;





	cs = intel_ring_begin(req, n_flex_regs * 2 + 4);

	cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4);

	if (IS_ERR(cs))

	if (IS_ERR(cs))

		return PTR_ERR(cs);

		return PTR_ERR(cs);





	*cs++ = MI_LOAD_REGISTER_IMM(n_flex_regs + 1);

	*cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1);





	*cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL);

	*cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL);

	*cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |

	*cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |