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Commit b2acd566 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add capacity dmips and dpc values for Lagoon"

parents 5f1431b5 60b00900

qcom/lagoon.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
@@ -71,6 +73,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {
@@ -100,6 +104,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {
@@ -129,6 +135,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {
@@ -159,6 +167,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {
@@ -188,6 +198,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {
@@ -217,6 +229,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <703>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {
@@ -255,6 +269,8 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			capacity-dmips-mhz = <1894>;

			dynamic-power-coefficient = <703>;

			cache-size = <0x10000>;

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {