[ARM] S3C64XX: Update TCFG for new timer divider settings. (b09bcdd4) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm/mach-s3c6400/include/mach/pwm-clock.h

0 → 100644

+56 −0

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			/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
			*
			* Copyright 2008 Openmoko, Inc.
			* Copyright 2008 Simtec Electronics
			* Ben Dooks <ben@simtec.co.uk>
			* http://armlinux.simtec.co.uk/
			*
			* S3C64xx - pwm clock and timer support
			*/

			/**
			* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
			* @tcfg: The timer TCFG1 register bits shifted down to 0.
			*
			* Return true if the given configuration from TCFG1 is a TCLK instead
			* any of the TDIV clocks.
			*/
			static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
			{
			return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
			}

			/**
			* tcfg_to_divisor() - convert tcfg1 setting to a divisor
			* @tcfg1: The tcfg1 setting, shifted down.
			*
			* Get the divisor value for the given tcfg1 setting. We assume the
			* caller has already checked to see if this is not a TCLK source.
			*/
			static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
			{
			return 1 << tcfg1;
			}

			/**
			* pwm_tdiv_has_div1() - does the tdiv setting have a /1
			*
			* Return true if we have a /1 in the tdiv setting.
			*/
			static inline unsigned int pwm_tdiv_has_div1(void)
			{
			return 1;
			}

			/**
			* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
			* @div: The divisor to calculate the bit information for.
			*
			* Turn a divisor into the necessary bit field for TCFG1.
			*/
			static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
			{
			return ilog2(div);
			}

			#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK

arch/arm/plat-s3c/include/plat/regs-timer.h

+8 −0

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	@@ -73,6 +73,14 @@
	#define S3C2410_TCFG1_MUX_TCLK (4<<0)		#define S3C2410_TCFG1_MUX_TCLK (4<<0)
	#define S3C2410_TCFG1_MUX_MASK (15<<0)		#define S3C2410_TCFG1_MUX_MASK (15<<0)

			#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
			#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
			#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
			#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
			#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
			#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
			#define S3C64XX_TCFG1_MUX_MASK (15<<0)

	#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)		#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)

	/* for each timer, we have an count buffer, an compare buffer and		/* for each timer, we have an count buffer, an compare buffer and

arch/arm/plat-s3c/pwm-clock.c

+10 −29

Original line number	Original line	Diff line number	Diff line
	@@ -14,6 +14,7 @@
	#include <linux/kernel.h>		#include <linux/kernel.h>
	#include <linux/list.h>		#include <linux/list.h>
	#include <linux/errno.h>		#include <linux/errno.h>
			#include <linux/log2.h>
	#include <linux/clk.h>		#include <linux/clk.h>
	#include <linux/err.h>		#include <linux/err.h>
	#include <linux/io.h>		#include <linux/io.h>
	@@ -26,6 +27,7 @@
	#include <plat/cpu.h>		#include <plat/cpu.h>

	#include <plat/regs-timer.h>		#include <plat/regs-timer.h>
			#include <mach/pwm-clock.h>

	/* Each of the timers 0 through 5 go through the following		/* Each of the timers 0 through 5 go through the following
	* clock tree, with the inputs depending on the timers.		* clock tree, with the inputs depending on the timers.
	@@ -166,11 +168,6 @@ static inline struct pwm_tdiv_clk to_tdiv(struct clk clk)
	return container_of(clk, struct pwm_tdiv_clk, clk);		return container_of(clk, struct pwm_tdiv_clk, clk);
	}		}

	static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
	{
	return 1 << (1 + tcfg1);
	}

	static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)		static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
	{		{
	unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);		unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
	@@ -179,7 +176,7 @@ static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
	tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);		tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
	tcfg1 &= S3C2410_TCFG1_MUX_MASK;		tcfg1 &= S3C2410_TCFG1_MUX_MASK;

	if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)		if (pwm_cfg_src_is_tclk(tcfg1))
	divisor = to_tdiv(clk)->divisor;		divisor = to_tdiv(clk)->divisor;
	else		else
	divisor = tcfg_to_divisor(tcfg1);		divisor = tcfg_to_divisor(tcfg1);
	@@ -196,7 +193,9 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
	parent_rate = clk_get_rate(clk->parent);		parent_rate = clk_get_rate(clk->parent);
	divisor = parent_rate / rate;		divisor = parent_rate / rate;

	if (divisor <= 2)		if (divisor <= 1 && pwm_tdiv_has_div1())
			divisor = 1;
			else if (divisor <= 2)
	divisor = 2;		divisor = 2;
	else if (divisor <= 4)		else if (divisor <= 4)
	divisor = 4;		divisor = 4;
	@@ -210,25 +209,7 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,

	static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)		static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
	{		{
	unsigned long bits;		return pwm_tdiv_div_bits(divclk->divisor);

	switch (divclk->divisor) {
	case 2:
	bits = S3C2410_TCFG1_MUX_DIV2;
	break;
	case 4:
	bits = S3C2410_TCFG1_MUX_DIV4;
	break;
	case 8:
	bits = S3C2410_TCFG1_MUX_DIV8;
	break;
	case 16:
	default:
	bits = S3C2410_TCFG1_MUX_DIV16;
	break;
	}

	return bits;
	}		}

	static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)		static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
	@@ -269,7 +250,7 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
	/* Update the current MUX settings if we are currently		/* Update the current MUX settings if we are currently
	* selected as the clock source for this clock. */		* selected as the clock source for this clock. */

	if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)		if (!pwm_cfg_src_is_tclk(tcfg1))
	clk_pwm_tdiv_update(divclk);		clk_pwm_tdiv_update(divclk);

	return 0;		return 0;
	@@ -356,7 +337,7 @@ static int clk_pwm_tin_set_parent(struct clk clk, struct clk parent)
	unsigned long shift = S3C2410_TCFG1_SHIFT(id);		unsigned long shift = S3C2410_TCFG1_SHIFT(id);

	if (parent == s3c24xx_pwmclk_tclk(id))		if (parent == s3c24xx_pwmclk_tclk(id))
	bits = S3C2410_TCFG1_MUX_TCLK << shift;		bits = S3C_TCFG1_MUX_TCLK << shift;
	else if (parent == s3c24xx_pwmclk_tdiv(id))		else if (parent == s3c24xx_pwmclk_tdiv(id))
	bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;		bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
	else		else
	@@ -418,7 +399,7 @@ static __init int clk_pwm_tin_register(struct clk *pwm)
	tcfg1 >>= S3C2410_TCFG1_SHIFT(id);		tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
	tcfg1 &= S3C2410_TCFG1_MUX_MASK;		tcfg1 &= S3C2410_TCFG1_MUX_MASK;

	if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)		if (pwm_cfg_src_is_tclk(tcfg1))
	parent = s3c24xx_pwmclk_tclk(id);		parent = s3c24xx_pwmclk_tclk(id);
	else		else
	parent = s3c24xx_pwmclk_tdiv(id);		parent = s3c24xx_pwmclk_tdiv(id);

arch/arm/plat-s3c24xx/include/mach/pwm-clock.h

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			/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
			*
			* Copyright 2008 Simtec Electronics
			* Ben Dooks <ben@simtec.co.uk>
			* http://armlinux.simtec.co.uk/
			*
			* S3C24xx - pwm clock and timer support
			*/

			/**
			* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
			* @cfg: The timer TCFG1 register bits shifted down to 0.
			*
			* Return true if the given configuration from TCFG1 is a TCLK instead
			* any of the TDIV clocks.
			*/
			static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
			{
			return tcfg == S3C2410_TCFG1_MUX_TCLK;
			}

			/**
			* tcfg_to_divisor() - convert tcfg1 setting to a divisor
			* @tcfg1: The tcfg1 setting, shifted down.
			*
			* Get the divisor value for the given tcfg1 setting. We assume the
			* caller has already checked to see if this is not a TCLK source.
			*/
			static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
			{
			return 1 << (1 + tcfg1);
			}

			/**
			* pwm_tdiv_has_div1() - does the tdiv setting have a /1
			*
			* Return true if we have a /1 in the tdiv setting.
			*/
			static inline unsigned int pwm_tdiv_has_div1(void)
			{
			return 0;
			}

			/**
			* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
			* @div: The divisor to calculate the bit information for.
			*
			* Turn a divisor into the necessary bit field for TCFG1.
			*/
			static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
			{
			return ilog2(div) - 1;
			}

			#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK