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Commit 44539a71 authored by Ben Dooks's avatar Ben Dooks
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[ARM] S3C64XX: Fix MMC0 clock source register mask 



Fix the definition of the MMC0 register shift and mask in the
CLKSRC register.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 6a5f4b85

arch/arm/plat-s3c64xx/include/plat/regs-clock.h

+2 −2
Original line number Diff line number Diff line
@@ -205,8 +205,8 @@ 
#define S3C6400_CLKSRC_MMC2_SHIFT	(22)

#define S3C6400_CLKSRC_MMC1_MASK	(0x3 << 20)

#define S3C6400_CLKSRC_MMC1_SHIFT	(20)

#define S3C6400_CLKSRC_MMC0_MASK	(0xf << 1)

#define S3C6400_CLKSRC_MMC0_SHIFT	(1)

#define S3C6400_CLKSRC_MMC0_MASK	(0x3 << 18)

#define S3C6400_CLKSRC_MMC0_SHIFT	(18)

#define S3C6400_CLKSRC_SPI1_MASK	(0x3 << 16)

#define S3C6400_CLKSRC_SPI1_SHIFT	(16)

#define S3C6400_CLKSRC_SPI0_MASK	(0x3 << 14)