Loading drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -58,6 +58,7 @@ #define A6XX_CP_SQE_INSTR_BASE_LO 0x830 #define A6XX_CP_SQE_INSTR_BASE_HI 0x831 #define A6XX_CP_MISC_CNTL 0x840 #define A6XX_CP_APRIV_CNTL 0X844 #define A6XX_CP_ROQ_THRESHOLDS_1 0x8C1 #define A6XX_CP_ROQ_THRESHOLDS_2 0x8C2 #define A6XX_CP_MEM_POOL_SIZE 0x8C3 Loading drivers/gpu/msm/adreno-gpulist.h +1 −0 Original line number Diff line number Diff line Loading @@ -454,6 +454,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .patchid = 0, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU, .sqefw_name = "a650_sqe.fw", .zap_name = "a650_zap", .gpudev = &adreno_a6xx_gpudev, .gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */ .num_protected_regs = 0x30, Loading drivers/gpu/msm/adreno_a6xx.c +9 −0 Original line number Diff line number Diff line Loading @@ -1294,6 +1294,15 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, if (ret) return ret; /* * Set the RBPRIVLEVEL bit in this register to determine * the privilege level of ucode executing packets in the RB, * so we can come out of secure mode and CP does not drop * the packet. */ if (adreno_is_a650(adreno_dev)) kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, (1 << 2)); /* Clear the SQE_HALT to start the CP engine */ kgsl_regwrite(device, A6XX_CP_SQE_CNTL, 1); Loading Loading
drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -58,6 +58,7 @@ #define A6XX_CP_SQE_INSTR_BASE_LO 0x830 #define A6XX_CP_SQE_INSTR_BASE_HI 0x831 #define A6XX_CP_MISC_CNTL 0x840 #define A6XX_CP_APRIV_CNTL 0X844 #define A6XX_CP_ROQ_THRESHOLDS_1 0x8C1 #define A6XX_CP_ROQ_THRESHOLDS_2 0x8C2 #define A6XX_CP_MEM_POOL_SIZE 0x8C3 Loading
drivers/gpu/msm/adreno-gpulist.h +1 −0 Original line number Diff line number Diff line Loading @@ -454,6 +454,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .patchid = 0, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU, .sqefw_name = "a650_sqe.fw", .zap_name = "a650_zap", .gpudev = &adreno_a6xx_gpudev, .gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */ .num_protected_regs = 0x30, Loading
drivers/gpu/msm/adreno_a6xx.c +9 −0 Original line number Diff line number Diff line Loading @@ -1294,6 +1294,15 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, if (ret) return ret; /* * Set the RBPRIVLEVEL bit in this register to determine * the privilege level of ucode executing packets in the RB, * so we can come out of secure mode and CP does not drop * the packet. */ if (adreno_is_a650(adreno_dev)) kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, (1 << 2)); /* Clear the SQE_HALT to start the CP engine */ kgsl_regwrite(device, A6XX_CP_SQE_CNTL, 1); Loading