Merge "drm/msm/dp: use scaled up mvid/nvid values" (a281f86a) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/drm/msm/dp/dp_catalog.c

+26 −46

Original line number	Diff line number	Diff line
		@@ -952,12 +952,10 @@ static void dp_catalog_panel_config_misc(struct dp_catalog_panel *panel)
		}

		static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
		u32 rate, u32 stream_rate_khz,
		bool fixed_nvid)
		u32 rate, u32 stream_rate_khz)
		{
		u32 pixel_m, pixel_n;
		u32 mvid, nvid;
		u64 mvid_calc;
		u32 const nvid_fixed = 0x8000;
		u32 const link_rate_hbr2 = 540000;
		u32 const link_rate_hbr3 = 810000;
		@@ -977,31 +975,6 @@ static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
		}

		catalog = dp_catalog_get_priv(panel);
		if (fixed_nvid) {
		pr_debug("use fixed NVID=0x%x\n", nvid_fixed);
		nvid = nvid_fixed;

		pr_debug("link rate=%dkbps, stream_rate_khz=%uKhz\n",
		rate, stream_rate_khz);

		/*
		* For intermediate results, use 64 bit arithmetic to avoid
		* loss of precision.
		*/
		mvid_calc = (u64) stream_rate_khz * nvid;
		mvid_calc = div_u64(mvid_calc, rate);

		/*
		* truncate back to 32 bits as this final divided value will
		* always be within the range of a 32 bit unsigned int.
		*/
		mvid = (u32) mvid_calc;

		if (panel->widebus_en) {
		mvid <<= 1;
		nvid <<= 1;
		}
		} else {
		io_data = catalog->io.dp_mmss_cc;

		if (panel->stream_id == DP_STREAM_1)
		@@ -1016,6 +989,14 @@ static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,
		mvid = (pixel_m & 0xFFFF) * 5;
		nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);

		if (nvid < nvid_fixed) {
		u32 temp;

		temp = (nvid_fixed / nvid) * nvid;
		mvid = (nvid_fixed / nvid) * mvid;
		nvid = temp;
		}

		pr_debug("rate = %d\n", rate);

		if (panel->widebus_en)
		@@ -1026,7 +1007,6 @@ static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel,

		if (link_rate_hbr3 == rate)
		nvid *= 3;
		}

		io_data = catalog->io.dp_link;

drivers/gpu/drm/msm/dp/dp_catalog.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -223,7 +223,7 @@ struct dp_catalog_panel {
		void (config_spd)(struct dp_catalog_panel panel);
		void (config_misc)(struct dp_catalog_panel panel);
		void (config_msa)(struct dp_catalog_panel panel,
		u32 rate, u32 stream_rate_khz, bool fixed_nvid);
		u32 rate, u32 stream_rate_khz);
		void (update_transfer_unit)(struct dp_catalog_panel panel);
		void (config_ctrl)(struct dp_catalog_panel panel, u32 cfg);
		void (config_dto)(struct dp_catalog_panel panel, bool ack);

drivers/gpu/drm/msm/dp/dp_catalog_v200.c

+27 −47

Original line number	Diff line number	Diff line
		@@ -118,12 +118,10 @@ static void dp_catalog_aux_setup_v200(struct dp_catalog_aux *aux,
		}

		static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel,
		u32 rate, u32 stream_rate_khz,
		bool fixed_nvid)
		u32 rate, u32 stream_rate_khz)
		{
		u32 pixel_m, pixel_n;
		u32 mvid, nvid;
		u64 mvid_calc;
		u32 const nvid_fixed = 0x8000;
		u32 const link_rate_hbr2 = 540000;
		u32 const link_rate_hbr3 = 810000;
		@@ -143,31 +141,6 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel,
		}

		catalog = dp_catalog_get_priv_v200(panel);
		if (fixed_nvid) {
		pr_debug("use fixed NVID=0x%x\n", nvid_fixed);
		nvid = nvid_fixed;

		pr_debug("link rate=%dkbps, stream_rate_khz=%uKhz\n",
		rate, stream_rate_khz);

		/*
		* For intermediate results, use 64 bit arithmetic to avoid
		* loss of precision.
		*/
		mvid_calc = (u64) stream_rate_khz * nvid;
		mvid_calc = div_u64(mvid_calc, rate);

		/*
		* truncate back to 32 bits as this final divided value will
		* always be within the range of a 32 bit unsigned int.
		*/
		mvid = (u32) mvid_calc;

		if (panel->widebus_en) {
		mvid <<= 1;
		nvid <<= 1;
		}
		} else {
		io_data = catalog->io->dp_mmss_cc;

		if (panel->stream_id == DP_STREAM_1)
		@@ -183,6 +156,14 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel,
		mvid = (pixel_m & 0xFFFF) * 5;
		nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);

		if (nvid < nvid_fixed) {
		u32 temp;

		temp = (nvid_fixed / nvid) * nvid;
		mvid = (nvid_fixed / nvid) * mvid;
		nvid = temp;
		}

		pr_debug("rate = %d\n", rate);

		if (panel->widebus_en)
		@@ -193,7 +174,6 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel,

		if (link_rate_hbr3 == rate)
		nvid *= 3;
		}

		io_data = catalog->io->dp_link;

drivers/gpu/drm/msm/dp/dp_catalog_v420.c

+26 −46

Original line number	Diff line number	Diff line
		@@ -122,12 +122,10 @@ static void dp_catalog_aux_clear_hw_interrupts_v420(struct dp_catalog_aux *aux)
		}

		static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
		u32 rate, u32 stream_rate_khz,
		bool fixed_nvid)
		u32 rate, u32 stream_rate_khz)
		{
		u32 pixel_m, pixel_n;
		u32 mvid, nvid, reg_off = 0, mvid_off = 0, nvid_off = 0;
		u64 mvid_calc;
		u32 const nvid_fixed = 0x8000;
		u32 const link_rate_hbr2 = 540000;
		u32 const link_rate_hbr3 = 810000;
		@@ -145,31 +143,6 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
		}

		catalog = dp_catalog_get_priv_v420(panel);
		if (fixed_nvid) {
		pr_debug("use fixed NVID=0x%x\n", nvid_fixed);
		nvid = nvid_fixed;

		pr_debug("link rate=%dkbps, stream_rate_khz=%uKhz\n",
		rate, stream_rate_khz);

		/*
		* For intermediate results, use 64 bit arithmetic to avoid
		* loss of precision.
		*/
		mvid_calc = (u64) stream_rate_khz * nvid;
		mvid_calc = div_u64(mvid_calc, rate);

		/*
		* truncate back to 32 bits as this final divided value will
		* always be within the range of a 32 bit unsigned int.
		*/
		mvid = (u32) mvid_calc;

		if (panel->widebus_en) {
		mvid <<= 1;
		nvid <<= 1;
		}
		} else {
		io_data = catalog->io->dp_mmss_cc;

		if (panel->stream_id == DP_STREAM_1)
		@@ -184,6 +157,14 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
		mvid = (pixel_m & 0xFFFF) * 5;
		nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF);

		if (nvid < nvid_fixed) {
		u32 temp;

		temp = (nvid_fixed / nvid) * nvid;
		mvid = (nvid_fixed / nvid) * mvid;
		nvid = temp;
		}

		pr_debug("rate = %d\n", rate);

		if (panel->widebus_en)
		@@ -194,7 +175,6 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,

		if (link_rate_hbr3 == rate)
		nvid *= 3;
		}

		io_data = catalog->io->dp_link;

drivers/gpu/drm/msm/dp/dp_panel.c

+1 −26

Original line number	Diff line number	Diff line
		@@ -2760,47 +2760,22 @@ static void dp_panel_config_misc(struct dp_panel *dp_panel)
		catalog->config_misc(catalog);
		}

		static bool dp_panel_use_fixed_nvid(struct dp_panel *dp_panel)
		{
		u8 *dpcd = dp_panel->dpcd;
		struct sde_connector *c_conn = to_sde_connector(dp_panel->connector);

		/* use fixe mvid and nvid for MST streams */
		if (c_conn->mst_port)
		return true;

		/*
		* For better interop experience, used a fixed NVID=0x8000
		* whenever connected to a VGA dongle downstream.
		*/
		if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT) {
		u8 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
		DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG)
		return true;
		}

		return false;
		}

		static void dp_panel_config_msa(struct dp_panel *dp_panel)
		{
		struct dp_panel_private *panel;
		struct dp_catalog_panel *catalog;
		u32 rate;
		u32 stream_rate_khz;
		bool fixed_nvid;

		panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
		catalog = panel->catalog;

		catalog->widebus_en = dp_panel->widebus_en;

		fixed_nvid = dp_panel_use_fixed_nvid(dp_panel);
		rate = drm_dp_bw_code_to_link_rate(panel->link->link_params.bw_code);
		stream_rate_khz = dp_panel->pinfo.pixel_clk_khz;

		catalog->config_msa(catalog, rate, stream_rate_khz, fixed_nvid);
		catalog->config_msa(catalog, rate, stream_rate_khz);
		}

		static int dp_panel_hw_cfg(struct dp_panel *dp_panel, bool enable)