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Commit ad0561d4 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: dts: uniphier: use clock/reset controllers 



The UniPhier reset controller driver has been merged.  Enable it.
Also, replace the fixed-rate clocks with the dedicated clock
drivers.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 3bdba5ac

arch/arm/boot/dts/uniphier-common32.dtsi

+48 −5
Original line number Diff line number Diff line 
/*

 * Device Tree Source commonly used by UniPhier ARM SoCs

 *

 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>

 * Copyright (C) 2015-2016 Socionext Inc.

 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual
@@ -71,7 +72,7 @@ 
			interrupts = <0 33 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart0>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 0>;

		};



		serial1: serial@54006900 {
@@ -81,7 +82,7 @@ 
			interrupts = <0 35 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart1>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 1>;

		};



		serial2: serial@54006a00 {
@@ -91,7 +92,7 @@ 
			interrupts = <0 37 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart2>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 2>;

		};



		serial3: serial@54006b00 {
@@ -101,7 +102,7 @@ 
			interrupts = <0 177 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart3>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 3>;

		};



		system_bus: system-bus@58c00000 {
@@ -119,6 +120,34 @@ 
			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

			compatible = "socionext,uniphier-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

				#clock-cells = <1>;

			};



			mio_rst: reset {

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

				#clock-cells = <1>;

			};



			peri_rst: reset {

				#reset-cells = <1>;

			};

		};



		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;
@@ -149,6 +178,20 @@ 
				/* specify compatible in each SoC DTSI */

			};

		};



		sysctrl@61840000 {

			compatible = "socionext,uniphier-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x4000>;



			sys_clk: clock {

				#clock-cells = <1>;

			};



			sys_rst: reset {

				#reset-cells = <1>;

			};

		};

	};

};

arch/arm/boot/dts/uniphier-ld4.dtsi

+35 −16
Original line number Diff line number Diff line
@@ -67,18 +67,6 @@ 
			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};



		uart_clk: uart_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <36864000>;

		};



		iobus_clk: iobus_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <100000000>;

		};

	};

};
@@ -103,7 +91,7 @@ 
		interrupts = <0 41 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c0>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 4>;

		clock-frequency = <100000>;

	};
@@ -116,7 +104,7 @@ 
		interrupts = <0 42 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c1>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 5>;

		clock-frequency = <100000>;

	};
@@ -129,7 +117,7 @@ 
		interrupts = <0 43 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c2>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 6>;

		clock-frequency = <400000>;

	};
@@ -142,7 +130,7 @@ 
		interrupts = <0 44 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c3>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 7>;

		clock-frequency = <100000>;

	};
@@ -153,6 +141,8 @@ 
		interrupts = <0 80 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb0>;

		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;

		resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;

	};



	usb1: usb@5a810100 {
@@ -162,6 +152,8 @@ 
		interrupts = <0 81 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb1>;

		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;

		resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;

	};



	usb2: usb@5a820100 {
@@ -171,6 +163,8 @@ 
		interrupts = <0 82 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb2>;

		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;

		resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;

	};



};
@@ -183,6 +177,31 @@ 
	interrupts = <0 29 4>;

};



&mio_clk {

	compatible = "socionext,uniphier-ld4-mio-clock";

};



&mio_rst {

	compatible = "socionext,uniphier-ld4-mio-reset";

	resets = <&sys_rst 7>;

};



&peri_clk {

	compatible = "socionext,uniphier-ld4-peri-clock";

};



&peri_rst {

	compatible = "socionext,uniphier-ld4-peri-reset";

};



&pinctrl {

	compatible = "socionext,uniphier-ld4-pinctrl";

};



&sys_clk {

	compatible = "socionext,uniphier-ld4-clock";

};



&sys_rst {

	compatible = "socionext,uniphier-ld4-reset";

};

arch/arm/boot/dts/uniphier-pro4.dtsi

+35 −18
Original line number Diff line number Diff line
@@ -75,18 +75,6 @@ 
			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};



		uart_clk: uart_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <73728000>;

		};



		i2c_clk: i2c_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};

	};

};
@@ -111,7 +99,7 @@ 
		interrupts = <0 41 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c0>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 4>;

		clock-frequency = <100000>;

	};
@@ -124,7 +112,7 @@ 
		interrupts = <0 42 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c1>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 5>;

		clock-frequency = <100000>;

	};
@@ -137,7 +125,7 @@ 
		interrupts = <0 43 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c2>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 6>;

		clock-frequency = <100000>;

	};
@@ -150,7 +138,7 @@ 
		interrupts = <0 44 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c3>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 7>;

		clock-frequency = <100000>;

	};
@@ -163,7 +151,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 25 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 9>;

		clock-frequency = <400000>;

	};
@@ -174,7 +162,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 26 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 10>;

		clock-frequency = <400000>;

	};
@@ -185,6 +173,8 @@ 
		interrupts = <0 80 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb2>;

		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;

		resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;

	};



	usb3: usb@5a810100 {
@@ -194,6 +184,8 @@ 
		interrupts = <0 81 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb3>;

		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;

		resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;

	};

};
@@ -201,6 +193,31 @@ 
	clock-frequency = <25000000>;

};



&mio_clk {

	compatible = "socionext,uniphier-pro4-mio-clock";

};



&mio_rst {

	compatible = "socionext,uniphier-pro4-mio-reset";

	resets = <&sys_rst 7>;

};



&peri_clk {

	compatible = "socionext,uniphier-pro4-peri-clock";

};



&peri_rst {

	compatible = "socionext,uniphier-pro4-peri-reset";

};



&pinctrl {

	compatible = "socionext,uniphier-pro4-pinctrl";

};



&sys_clk {

	compatible = "socionext,uniphier-pro4-clock";

};



&sys_rst {

	compatible = "socionext,uniphier-pro4-reset";

};

arch/arm/boot/dts/uniphier-pro5.dtsi

+30 −18
Original line number Diff line number Diff line
@@ -75,18 +75,6 @@ 
			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};



		uart_clk: uart_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <73728000>;

		};



		i2c_clk: i2c_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};

	};

};
@@ -123,7 +111,7 @@ 
		interrupts = <0 41 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c0>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 4>;

		clock-frequency = <100000>;

	};
@@ -136,7 +124,7 @@ 
		interrupts = <0 42 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c1>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 5>;

		clock-frequency = <100000>;

	};
@@ -149,7 +137,7 @@ 
		interrupts = <0 43 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c2>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 6>;

		clock-frequency = <100000>;

	};
@@ -162,7 +150,7 @@ 
		interrupts = <0 44 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c3>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 7>;

		clock-frequency = <100000>;

	};
@@ -175,7 +163,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 25 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 9>;

		clock-frequency = <400000>;

	};
@@ -186,7 +174,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 26 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 10>;

		clock-frequency = <400000>;

	};

};
@@ -195,6 +183,30 @@ 
	clock-frequency = <20000000>;

};



&mio_clk {

	compatible = "socionext,uniphier-pro5-mio-clock";

};



&mio_rst {

	compatible = "socionext,uniphier-pro5-mio-reset";

};



&peri_clk {

	compatible = "socionext,uniphier-pro5-peri-clock";

};



&peri_rst {

	compatible = "socionext,uniphier-pro5-peri-reset";

};



&pinctrl {

	compatible = "socionext,uniphier-pro5-pinctrl";

};



&sys_clk {

	compatible = "socionext,uniphier-pro5-clock";

};



&sys_rst {

	compatible = "socionext,uniphier-pro5-reset";

};

arch/arm/boot/dts/uniphier-pxs2.dtsi

+31 −19
Original line number Diff line number Diff line
@@ -91,18 +91,6 @@ 
			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};



		uart_clk: uart_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <88900000>;

		};



		i2c_clk: i2c_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};

	};

};
@@ -127,7 +115,7 @@ 
		interrupts = <0 41 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c0>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 4>;

		clock-frequency = <100000>;

	};
@@ -140,7 +128,7 @@ 
		interrupts = <0 42 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c1>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 5>;

		clock-frequency = <100000>;

	};
@@ -153,7 +141,7 @@ 
		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c2>;

		interrupts = <0 43 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 6>;

		clock-frequency = <100000>;

	};
@@ -166,7 +154,7 @@ 
		interrupts = <0 44 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c3>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 7>;

		clock-frequency = <100000>;

	};
@@ -177,7 +165,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 45 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 8>;

		clock-frequency = <400000>;

	};
@@ -188,7 +176,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 25 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 9>;

		clock-frequency = <400000>;

	};
@@ -199,7 +187,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <0 26 4>;

		clocks = <&i2c_clk>;

		clocks = <&peri_clk 10>;

		clock-frequency = <400000>;

	};

};
@@ -208,6 +196,30 @@ 
	clock-frequency = <25000000>;

};



&mio_clk {

	compatible = "socionext,uniphier-pxs2-mio-clock";

};



&mio_rst {

	compatible = "socionext,uniphier-pxs2-mio-reset";

};



&peri_clk {

	compatible = "socionext,uniphier-pxs2-peri-clock";

};



&peri_rst {

	compatible = "socionext,uniphier-pxs2-peri-reset";

};



&pinctrl {

	compatible = "socionext,uniphier-pxs2-pinctrl";

};



&sys_clk {

	compatible = "socionext,uniphier-pxs2-clock";

};



&sys_rst {

	compatible = "socionext,uniphier-pxs2-reset";

};