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Commit 3bdba5ac authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: dts: uniphier: switch over to PSCI 



Use PSCI for enable-method instead of SoC specific implementation.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 77896e4d

arch/arm/boot/dts/uniphier-common32.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -45,6 +45,11 @@ 
/include/ "skeleton.dtsi"



/ {

	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	clocks {

		refclk: ref {

			#clock-cells = <0>;

arch/arm/boot/dts/uniphier-ld4.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};

	};

arch/arm/boot/dts/uniphier-pro4.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -51,12 +51,12 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "socionext,uniphier-smp";



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};
@@ -64,6 +64,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};

	};

arch/arm/boot/dts/uniphier-pro5.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -51,12 +51,12 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "socionext,uniphier-smp";



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};
@@ -64,6 +64,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};

	};

arch/arm/boot/dts/uniphier-pxs2.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -51,12 +51,12 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "socionext,uniphier-smp";



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};
@@ -64,6 +64,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};
@@ -71,6 +72,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <2>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};
@@ -78,6 +80,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <3>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};

	};