Loading asoc/codecs/sdm660_cdc/msm-digital-cdc.c +4 −3 Original line number Diff line number Diff line Loading @@ -93,11 +93,12 @@ static int msm_digcdc_clock_control(bool flag) __func__); /* * Avoid access to lpass register * as clock enable failed during SSR. * as clock enable failed during SSR/PDR. */ if (ret == -ENODEV) msm_dig_cdc->regmap->cache_only = true; return ret; } else { msm_dig_cdc->regmap->cache_only = false; } pr_debug("enabled digital codec core clk\n"); atomic_set(&pdata->int_mclk0_enabled, true); Loading Loading
asoc/codecs/sdm660_cdc/msm-digital-cdc.c +4 −3 Original line number Diff line number Diff line Loading @@ -93,11 +93,12 @@ static int msm_digcdc_clock_control(bool flag) __func__); /* * Avoid access to lpass register * as clock enable failed during SSR. * as clock enable failed during SSR/PDR. */ if (ret == -ENODEV) msm_dig_cdc->regmap->cache_only = true; return ret; } else { msm_dig_cdc->regmap->cache_only = false; } pr_debug("enabled digital codec core clk\n"); atomic_set(&pdata->int_mclk0_enabled, true); Loading