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Commit ac3750e9 authored by Jagan Teki's avatar Jagan Teki Committed by Greg Kroah-Hartman
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clk: sunxi-ng: a64: Fix gate bit of DSI DPHY 



[ Upstream commit ee678706e46d0d185c27cc214ad97828e0643159 ]

DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.

Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent a26a4469

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+1 −1
Original line number Diff line number Diff line
@@ -582,7 +582,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; 
static const u8 dsi_dphy_table[] = { 0, 2, };

static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",

				       dsi_dphy_parents, dsi_dphy_table,

				       0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT);

				       0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);



static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",

			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);