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Commit a7c66cd8 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Assume 400MHz cdclk for the rest of gen4-7 



We don't currently have cdclk extraction code for 965g,snb,ivb.
Let's assume 400 MHz until we know better. That seems to match hints
in various vague documents. Whether that's good enough is not
entirely clear.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Acked-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b37a6434

drivers/gpu/drm/i915/intel_display.c

+2 −1
Original line number Diff line number Diff line
@@ -13506,7 +13506,8 @@ static void intel_init_display(struct drm_device *dev) 
	else if (IS_GEN5(dev))

		dev_priv->display.get_display_clock_speed =

			ilk_get_display_clock_speed;

	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))

	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||

		 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))

		dev_priv->display.get_display_clock_speed =

			i945_get_display_clock_speed;

	else if (IS_I915G(dev))