Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a3750a64 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Boris Brezillon
Browse files

mtd: nand: denali: support two row address cycle devices 



The register TWO_ROW_ADDR_CYCLES specifies the number of row address
cycles of the device, but it is fixed to 0 in the driver init code
(i.e. always 3 row address cycles).

Reflect the result of nand_scan_ident() to the register setting
in order to support 2 row address cycle devices.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent 14157f86

drivers/mtd/nand/denali.c

+2 −2
Original line number Diff line number Diff line
@@ -1137,8 +1137,6 @@ static void denali_hw_init(struct denali_nand_info *denali) 


	iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);



	/* Should set value for these registers when init */

	iowrite32(0, denali->reg + TWO_ROW_ADDR_CYCLES);

	iowrite32(1, denali->reg + ECC_ENABLE);

}
@@ -1379,6 +1377,8 @@ int denali_init(struct denali_nand_info *denali) 
		  denali->reg + PAGES_PER_BLOCK);

	iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,

		  denali->reg + DEVICE_WIDTH);

	iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,

		  denali->reg + TWO_ROW_ADDR_CYCLES);

	iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);

	iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);