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Commit a32e252f authored by Michael Neuling's avatar Michael Neuling Committed by Benjamin Herrenschmidt
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powerpc: Use new CPU feature bit to select 2.06 tlbie 



This removes MMU_FTR_TLBIE_206 as we can now use CPU_FTR_HVMODE_206.  It
also changes the logic to select which tlbie to use to be based on this
new CPU feature bit.

This also duplicates the ASM_FTR_IF/SET/CLR defines for CPU features
(copied from MMU features).

Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent 476eb491

arch/powerpc/include/asm/feature-fixups.h

+13 −0
Original line number Diff line number Diff line
@@ -146,6 +146,19 @@ label##5: \ 


#ifndef __ASSEMBLY__



#define ASM_FTR_IF(section_if, section_else, msk, val)	\

	stringify_in_c(BEGIN_FTR_SECTION)			\

	section_if "; "						\

	stringify_in_c(FTR_SECTION_ELSE)			\

	section_else "; "					\

	stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))



#define ASM_FTR_IFSET(section_if, section_else, msk)	\

	ASM_FTR_IF(section_if, section_else, (msk), (msk))



#define ASM_FTR_IFCLR(section_if, section_else, msk)	\

	ASM_FTR_IF(section_if, section_else, (msk), 0)



#define ASM_MMU_FTR_IF(section_if, section_else, msk, val)	\

	stringify_in_c(BEGIN_MMU_FTR_SECTION)			\

	section_if "; "						\

arch/powerpc/include/asm/mmu.h

+1 −7
Original line number Diff line number Diff line
@@ -56,11 +56,6 @@ 
 */

#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)



/* This indicates that the processor uses the ISA 2.06 server tlbie

 * mnemonics

 */

#define MMU_FTR_TLBIE_206		ASM_CONST(0x00400000)



/* Enable use of TLB reservation.  Processor should support tlbsrx.

 * instruction and MAS0[WQ].

 */
@@ -105,8 +100,7 @@ 
#define MMU_FTRS_PPC970		MMU_FTRS_POWER4

#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \

				MMU_FTR_TLBIE_206

#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \

				MMU_FTR_CI_LARGE_PAGE

#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \

arch/powerpc/mm/hash_native_64.c

+4 −6
Original line number Diff line number Diff line
@@ -50,9 +50,8 @@ static inline void __tlbie(unsigned long va, int psize, int ssize) 
	case MMU_PAGE_4K:

		va &= ~0xffful;

		va |= ssize << 8;

		asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),

					       %2)

			     : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)

		asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)

			     : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)

			     : "memory");

		break;

	default:
@@ -61,9 +60,8 @@ static inline void __tlbie(unsigned long va, int psize, int ssize) 
		va |= penc << 12;

		va |= ssize << 8;

		va |= 1; /* L */

		asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),

					       %2)

			     : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)

		asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)

			     : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)

			     : "memory");

		break;

	}