Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a1aacc97 authored by Frank Min's avatar Frank Min Committed by Alex Deucher
Browse files

drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOV 



Optimize init table sequence for sriov.

Signed-off-by: default avatarFrank Min <Frank.Min@amd.com>
Signed-off-by: default avatarXiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4ed11d79

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

+2 −1
Original line number Diff line number Diff line
@@ -278,7 +278,8 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) 


		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);

		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),

						   0xffffffff, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);

						   VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,

						   VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);



		/* end of MC_RESUME */

		MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),