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Commit 9e7eaac9 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Ingo Molnar
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perf/x86/intel/cqm: Remove pointless spinlock from state cache 



'struct intel_cqm_state' is a strict per CPU cache of the rmid and the
usage counter. It can never be modified from a remote CPU.

The three functions which modify the content: intel_cqm_event[start|stop|del]
(del maps to stop) are called from the perf core with interrupts disabled
which is enough protection for the per CPU state values.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarMatt Fleming <matt.fleming@intel.com>
Cc: Kanaka Juvva <kanaka.d.juvva@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: Will Auld <will.auld@intel.com>
Link: http://lkml.kernel.org/r/20150518235150.001006529@linutronix.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent b3df4ec4

arch/x86/kernel/cpu/perf_event_intel_cqm.c

+6 −11
Original line number Diff line number Diff line
@@ -17,11 +17,16 @@ static unsigned int cqm_max_rmid = -1; 
static unsigned int cqm_l3_scale; /* supposedly cacheline size */



struct intel_cqm_state {

	raw_spinlock_t		lock;

	u32			rmid;

	int			cnt;

};



/*

 * The cached intel_cqm_state is strictly per CPU and can never be

 * updated from a remote CPU. Both functions which modify the state

 * (intel_cqm_event_start and intel_cqm_event_stop) are called with

 * interrupts disabled, which is sufficient for the protection.

 */

static DEFINE_PER_CPU(struct intel_cqm_state, cqm_state);



/*
@@ -963,15 +968,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode) 
{

	struct intel_cqm_state *state = this_cpu_ptr(&cqm_state);

	u32 rmid = event->hw.cqm_rmid;

	unsigned long flags;



	if (!(event->hw.cqm_state & PERF_HES_STOPPED))

		return;



	event->hw.cqm_state &= ~PERF_HES_STOPPED;



	raw_spin_lock_irqsave(&state->lock, flags);



	if (state->cnt++)

		WARN_ON_ONCE(state->rmid != rmid);

	else
@@ -984,21 +986,17 @@ static void intel_cqm_event_start(struct perf_event *event, int mode) 
	 * Technology component.

	 */

	wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0);



	raw_spin_unlock_irqrestore(&state->lock, flags);

}



static void intel_cqm_event_stop(struct perf_event *event, int mode)

{

	struct intel_cqm_state *state = this_cpu_ptr(&cqm_state);

	unsigned long flags;



	if (event->hw.cqm_state & PERF_HES_STOPPED)

		return;



	event->hw.cqm_state |= PERF_HES_STOPPED;



	raw_spin_lock_irqsave(&state->lock, flags);

	intel_cqm_event_read(event);



	if (!--state->cnt) {
@@ -1013,8 +1011,6 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode) 
	} else {

		WARN_ON_ONCE(!state->rmid);

	}



	raw_spin_unlock_irqrestore(&state->lock, flags);

}



static int intel_cqm_event_add(struct perf_event *event, int mode)
@@ -1257,7 +1253,6 @@ static void intel_cqm_cpu_prepare(unsigned int cpu) 
	struct intel_cqm_state *state = &per_cpu(cqm_state, cpu);

	struct cpuinfo_x86 *c = &cpu_data(cpu);



	raw_spin_lock_init(&state->lock);

	state->rmid = 0;

	state->cnt  = 0;