Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 99a41011 authored by Roger Quadros's avatar Roger Quadros Committed by Tony Lindgren
Browse files

ARM: dts: am437x: Provide NAND ready pin 



On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.

Read speed increases from 16516 KiB/ to 18813 KiB/s
and write speed was unchanged at 9941 KiB/s.

Measured using mtd_speedtest.ko.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent a23fc155

arch/arm/boot/dts/am437x-gp-evm.dts

+1 −0
Original line number Diff line number Diff line
@@ -817,6 +817,7 @@ 
		interrupt-parent = <&gpmc>;

		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */

			     <1 IRQ_TYPE_NONE>;	/* termcount */

		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */

		ti,nand-ecc-opt = "bch16";

		ti,elm-id = <&elm>;

		nand-bus-width = <8>;

arch/arm/boot/dts/am43x-epos-evm.dts

+1 −0
Original line number Diff line number Diff line
@@ -568,6 +568,7 @@ 
		interrupt-parent = <&gpmc>;

		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */

			     <1 IRQ_TYPE_NONE>;	/* termcount */

		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */

		ti,nand-ecc-opt = "bch16";

		ti,elm-id = <&elm>;

		nand-bus-width = <8>;