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Commit a23fc155 authored Apr 07, 2016 by Roger Quadros Committed by Tony Lindgren Apr 12, 2016

ARM: dts: dra7x-evm: Provide NAND ready pin



On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.

Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

parent 8675afe5

arch/arm/boot/dts/dra7-evm.dts

+1 −0

Original line number	Diff line number	Diff line
		@@ -776,6 +776,7 @@
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
		<1 IRQ_TYPE_NONE>; /* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;

arch/arm/boot/dts/dra72-evm.dts

+1 −0

Original line number	Diff line number	Diff line
		@@ -503,6 +503,7 @@
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
		<1 IRQ_TYPE_NONE>; /* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;