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Commit 9057c23e authored by Taniya Das's avatar Taniya Das Committed by Chetan C R
Browse files

clk: qcom: clk-pll: Add support for SPM event in PLL 



Add SPM event support for CPU clocks in Pll.

Change-Id: I8d6edcaf0dd666319b7be9d3f8001d2b0c7a165b
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 5347ec32

drivers/clk/qcom/clk-pll.c

+51 −2
Original line number Diff line number Diff line
@@ -29,6 +29,44 @@ 
#define PLL_BYPASSNL		BIT(1)

#define PLL_RESET_N		BIT(2)



static void spm_event(void __iomem *base, u32 offset, u32 bit, bool enable)

{

	uint32_t val;



	if (!base)

		return;



	if (enable) {

		/* L2_SPM_FORCE_EVENT_EN */

		val = readl_relaxed(base + offset);

		val |= BIT(bit);

		writel_relaxed(val, (base + offset));

		/* Ensure that the write above goes through. */

		mb();



		/* L2_SPM_FORCE_EVENT */

		val = readl_relaxed(base + offset + 0x4);

		val |= BIT(bit);

		writel_relaxed(val, (base + offset + 0x4));

		/* Ensure that the write above goes through. */

		mb();

	} else {

		/* L2_SPM_FORCE_EVENT */

		val = readl_relaxed(base + offset + 0x4);

		val &= ~BIT(bit);

		writel_relaxed(val, (base + offset + 0x4));

		/* Ensure that the write above goes through. */

		mb();



		/* L2_SPM_FORCE_EVENT_EN */

		val = readl_relaxed(base + offset);

		val &= ~BIT(bit);

		writel_relaxed(val, (base + offset));

		/* Ensure that the write above goes through. */

		mb();

	}

}



static int clk_pll_enable(struct clk_hw *hw)

{

	struct clk_pll *pll = to_clk_pll(hw);
@@ -76,6 +114,9 @@ static void clk_pll_disable(struct clk_hw *hw) 
	u32 mask;

	u32 val;



	spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,

			pll->spm_ctrl.event_bit, true);



	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);

	/* Skip if in FSM mode */

	if (val & PLL_VOTE_FSM_ENA)
@@ -219,7 +260,7 @@ static int wait_for_pll(struct clk_pll *pll) 
	const char *name = clk_hw_get_name(&pll->clkr.hw);



	/* Wait for pll to enable. */

	for (count = 200; count > 0; count--) {

	for (count = 500; count > 0; count--) {

		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);

		if (ret)

			return ret;
@@ -228,7 +269,8 @@ static int wait_for_pll(struct clk_pll *pll) 
		udelay(1);

	}



	WARN(1, "%s didn't enable after voting for it!\n", name);

	WARN_CLK(pll->clkr.hw.core, name, 1,

			"didn't enable after voting for it!\n");

	return -ETIMEDOUT;

}
@@ -301,6 +343,9 @@ static int clk_pll_sr2_enable(struct clk_hw *hw) 
	int ret;

	u32 mode;



	spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,

			pll->spm_ctrl.event_bit, false);



	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);

	if (ret)

		return ret;
@@ -323,6 +368,10 @@ static int clk_pll_sr2_enable(struct clk_hw *hw) 
	if (ret)

		return ret;



	/* Make sure De-assert active-low PLL reset request goes through */

	mb();

	udelay(50);



	ret = wait_for_pll(pll);

	if (ret)

		return ret;

drivers/clk/qcom/clk-pll.h

+7 −0
Original line number Diff line number Diff line
@@ -32,6 +32,12 @@ struct pll_freq_tbl { 
	u32 ibits;

};



struct pll_spm_ctrl {

	u32 offset;

	u32 event_bit;

	void __iomem *spm_base;

};



/**

 * struct clk_pll - phase locked loop (PLL)

 * @l_reg: L register
@@ -58,6 +64,7 @@ struct clk_pll { 
	const struct pll_freq_tbl *freq_tbl;



	struct clk_regmap clkr;

	struct pll_spm_ctrl spm_ctrl;

};



extern const struct clk_ops clk_pll_ops;