Commit 8e7a65aa authored Oct 07, 2015 by Ville Syrjälä Committed by Jani Nikula Oct 13, 2015

drm/i915: Restore lost DPLL register write on gen2-4



We accidentally lost the initial DPLL register write in
1c4e0274 drm/i915: Fix DVO 2x clock enable on 830M

The "three times for luck" hack probably saved us from a total
disaster. But anyway, bring the initial write back so that the
code actually makes some sense.

Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
References: http://mid.gmane.org/CAN_QmVyMaArxYgEcVVsGvsMo7-6ohZr8HmF5VhkkL4i9KOmrhw@mail.gmail.com


Cc: stable@vger.kernel.org
Cc: Nick Bowler <nbowler@draconx.ca>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

parent 40a24488

drivers/gpu/drm/i915/intel_display.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -1724,6 +1724,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
		I915_READ(DPLL(!crtc->pipe)) \| DPLL_DVO_2X_MODE);
		}

		I915_WRITE(reg, dpll);

		/* Wait for the clocks to stabilize. */
		POSTING_READ(reg);
		udelay(150);