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Commit 40a24488 authored by Chris Wilson's avatar Chris Wilson Committed by Jani Nikula
Browse files

drm/i915: Flush pipecontrol post-sync writes 



In order to flush the results from in-batch pipecontrol writes (used for
example in glQuery) before declaring the batch complete (and so declaring
the query results coherent), we need to set the FlushEnable bit in our
flushing pipecontrol. The FlushEnable bit "waits until all previous
writes of immediate data from post-sync circles are complete before
executing the next command".

I get GPU hangs on byt without flushing these writes (running ue4).
piglit has examples where the flush is required for correct rendering.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel@ffwll.ch>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent e797e4b7

drivers/gpu/drm/i915/intel_lrc.c

+1 −0
Original line number Diff line number Diff line
@@ -1659,6 +1659,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, 
	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}



	if (invalidate_domains) {

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −0
Original line number Diff line number Diff line
@@ -347,6 +347,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, 
	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}

	if (invalidate_domains) {

		flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -418,6 +419,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req, 
	if (flush_domains) {

		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

	}

	if (invalidate_domains) {

		flags |= PIPE_CONTROL_TLB_INVALIDATE;