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Commit 85c41e2a authored by Jigarkumar Zala's avatar Jigarkumar Zala Committed by Gerrit - the friendly Code Review server
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msm: camera: csiphy: Clean up bringup seq for 3phase operation 



There are some register duplicated to program bringup sequence for
3phase opertion based on datarate. This change removes duplicate
register settings, as well as renaming some macros for code
readability.

Change-Id: Idb1f617ca1bb749e9875647074781c91a385ec3c
Signed-off-by: default avatarJigarkumar Zala <jzala@codeaurora.org>
parent 89e0ec90

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

+27 −27
Original line number Diff line number Diff line
@@ -255,8 +255,7 @@ struct cam_csiphy_param { 
 * @clk_lane:                   Clock lane

 * @acquire_count:              Acquire device count

 * @start_dev_count:            Start count

 * @is_acquired_dev_combo_mode:

 *    Flag that mentions whether already acquired

 * @is_acquired_dev_combo_mode: Flag that mentions whether already acquired

 *                              device is for combo mode

 * @soc_info:                   SOC information

 * @cpas_handle:                CPAS handle
@@ -275,6 +274,7 @@ struct csiphy_device { 
	int32_t ref_count;

	uint16_t lane_mask[MAX_CSIPHY];

	uint8_t is_csiphy_3phase_hw;

	uint8_t is_divisor_32_comp;

	uint8_t num_irq_registers;

	struct cam_subdev v4l2_dev_str;

	struct cam_csiphy_param csiphy_info;

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

+14 −9
Original line number Diff line number Diff line
@@ -11,9 +11,9 @@ 
#include "include/cam_csiphy_1_2_1_hwreg.h"

#include "include/cam_csiphy_2_0_hwreg.h"



#define CSIPHY_3PH_DIVISOR           16

#define CSIPHY_3PH_DIVISOR_12        32

#define CSIPHY_2PH_DIVISOR           8

#define CSIPHY_DIVISOR_16           16

#define CSIPHY_DIVISOR_32           32

#define CSIPHY_DIVISOR_8             8

#define BYTES_PER_REGISTER           4

#define NUM_REGISTER_PER_LINE        4

#define REG_OFFSET(__start, __i)    ((__start) + ((__i) * BYTES_PER_REGISTER))
@@ -96,12 +96,12 @@ enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev) 
			csiphy_dev->csiphy_info.data_rate_combo_sensor);



	if (csiphy_dev->csiphy_info.csiphy_3phase) {

		if (csiphy_dev->is_csiphy_3phase_hw == CSI_3PHASE_HW_12)

			do_div(phy_data_rate, CSIPHY_3PH_DIVISOR_12);

		if (csiphy_dev->is_divisor_32_comp)

			do_div(phy_data_rate, CSIPHY_DIVISOR_32);

		else

			do_div(phy_data_rate, CSIPHY_3PH_DIVISOR);

			do_div(phy_data_rate, CSIPHY_DIVISOR_16);

	} else {

		do_div(phy_data_rate, CSIPHY_2PH_DIVISOR);

		do_div(phy_data_rate, CSIPHY_DIVISOR_8);

	}



	 /* round off to next integer */
@@ -227,6 +227,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->hw_version = CSIPHY_VERSION_V10;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;

	} else if (of_device_is_compatible(soc_info->dev->of_node,
@@ -245,6 +246,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_1;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->hw_version = CSIPHY_VERSION_V11;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
@@ -262,7 +264,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
			csiphy_reset_reg_1_2;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW_12;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = true;

		csiphy_dev->hw_version = CSIPHY_VERSION_V12;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table =
@@ -281,7 +284,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
			csiphy_reset_reg_1_2_1;

		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_1;

		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW_12;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = true;

		csiphy_dev->hw_version = CSIPHY_VERSION_V121;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table =
@@ -300,6 +304,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;

		csiphy_dev->hw_version = CSIPHY_VERSION_V20;

		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;

	} else {

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h

+0 −1
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ 
#define CDBG(fmt, args...) pr_debug(fmt, ##args)



#define CSI_3PHASE_HW                               1

#define CSI_3PHASE_HW_12                          0x12

#define CSIPHY_VERSION_V35                        0x35

#define CSIPHY_VERSION_V10                        0x10

#define CSIPHY_VERSION_V11                        0x11

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h

+8 −17
Original line number Diff line number Diff line
@@ -12,10 +12,10 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { 
	.mipi_csiphy_interrupt_status0_addr = 0x8B0,

	.mipi_csiphy_interrupt_clear0_addr = 0x858,

	.mipi_csiphy_glbl_irq_cmd_addr = 0x828,

	.csiphy_common_array_size = 4,

	.csiphy_reset_array_size = 4,

	.csiphy_common_array_size = 6,

	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 21,

	.csiphy_3ph_config_array_size = 38,

	.csiphy_3ph_config_array_size = 34,

	.csiphy_2ph_clock_lane = 0x1,

	.csiphy_2ph_combo_ck_ln = 0x10,

};
@@ -23,14 +23,17 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { 
struct csiphy_reg_t csiphy_common_reg_1_2_1[] = {

	{0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE},

	{0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x02, 0x00, CSIPHY_2PH_REGS},

	{0x081C, 0x52, 0x00, CSIPHY_3PH_REGS},

	{0x0800, 0x02, 0x00, CSIPHY_2PH_REGS},

	{0x0800, 0x0E, 0x00, CSIPHY_3PH_REGS},

};



struct csiphy_reg_t csiphy_reset_reg_1_2_1[] = {

	{0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE},

	{0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

};
@@ -289,7 +292,6 @@ struct csiphy_reg_t 
struct

csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {

	{

		{0x015C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -298,7 +300,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x098C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0168, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x016C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x010C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},

		{0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -313,7 +314,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -325,11 +325,9 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

	{

		{0x035C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -338,7 +336,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0A98, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A8C, 0xBF, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0368, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x036C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x030C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},

		{0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -353,7 +350,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -365,11 +361,9 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0A88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

	{

		{0x055C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -378,7 +372,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0568, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x056C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x050C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},

		{0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -393,7 +386,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -405,7 +397,6 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0B88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

};