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Commit 89e0ec90 authored by Tony Lijo Jose's avatar Tony Lijo Jose Committed by Gerrit - the friendly Code Review server
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msm: camera: csiphy: Add multi data rate support



Add 2.5 gsps , 3.5 gsps , 4.5 gsps data rate supports for the
csiphy cphy 1.2 driver.

Change-Id: I9faaf62756f31cfb9cadfada63d4467c1429e0d2
Signed-off-by: default avatarTony Lijo Jose <tjose@codeaurora.org>
parent 1bba5c9f
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+62 −0
Original line number Diff line number Diff line
@@ -257,6 +257,65 @@ void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev)
			csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_addr);
}

void cam_csiphy_cphy_data_rate_config(struct csiphy_device *csiphy_device)
{
	int i = 0, j = 0;
	uint64_t phy_data_rate = 0;
	void __iomem *csiphybase = NULL;
	ssize_t num_table_entries = 0;
	struct data_rate_settings_t *settings_table = NULL;

	if ((csiphy_device == NULL) ||
		(csiphy_device->ctrl_reg == NULL) ||
		(csiphy_device->ctrl_reg->data_rates_settings_table == NULL)) {
		CAM_DBG(CAM_CSIPHY,
			"Data rate specific register table not found");
		return;
	}

	phy_data_rate = csiphy_device->csiphy_info.data_rate;
	csiphybase =
		csiphy_device->soc_info.reg_map[0].mem_base;
	settings_table =
		csiphy_device->ctrl_reg->data_rates_settings_table;
	num_table_entries =
		settings_table->num_data_rate_settings;

	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate);
	for (i = 0; i < num_table_entries; i++) {
		struct data_rate_reg_info_t *drate_settings =
			settings_table->data_rate_settings;
		uint64_t bandwidth =
			drate_settings[i].bandwidth;
		ssize_t  num_reg_entries =
		drate_settings[i].data_rate_reg_array_size;

		if (phy_data_rate > bandwidth) {
			CAM_DBG(CAM_CSIPHY,
					"Skipping table [%d] %llu required: %llu",
					i, bandwidth, phy_data_rate);
			continue;
		}

		CAM_DBG(CAM_CSIPHY,
			"table[%d] BW : %llu Selected", i, bandwidth);
		for (j = 0; j < num_reg_entries; j++) {
			uint32_t reg_addr =
			drate_settings[i].csiphy_data_rate_regs[j].reg_addr;

			uint32_t reg_data =
			drate_settings[i].csiphy_data_rate_regs[j].reg_data;

			CAM_DBG(CAM_CSIPHY,
				"writing reg : %x val : %x",
						reg_addr, reg_data);
			cam_io_w_mb(reg_data,
				csiphybase + reg_addr);
		}
		break;
	}
}

void cam_csiphy_cphy_irq_disable(struct csiphy_device *csiphy_dev)
{
	int32_t i;
@@ -464,6 +523,9 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev)
		lane_pos++;
	}

	if (csiphy_dev->csiphy_info.csiphy_3phase)
		cam_csiphy_cphy_data_rate_config(csiphy_dev);

	cam_csiphy_cphy_irq_config(csiphy_dev);

	return rc;
+32 −2
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@

#define MAX_LANES                   5
#define MAX_SETTINGS_PER_LANE       43
#define MAX_DATA_RATES              3
#define MAX_DATA_RATE_REGS          30

#define MAX_REGULATOR         5
#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"
@@ -147,6 +149,30 @@ struct csiphy_reg_t {

struct csiphy_device;

/*
 * struct data_rate_reg_info_t
 * @bandwidth: max bandwidth supported by this reg settings
 * @data_rate_reg_array_size: number of reg value pairs in the array
 * @csiphy_data_rate_regs: array of data rate specific reg value pairs
 */
struct data_rate_reg_info_t {
	uint64_t bandwidth;
	ssize_t  data_rate_reg_array_size;
	struct csiphy_reg_t csiphy_data_rate_regs[MAX_DATA_RATE_REGS];
};

/**
 * struct data_rate_settings_t
 * @num_data_rate_settings: number of valid settings
 *                          present in the data rate settings array
 * @data_rate_settings: array of regsettings which are specific to
 *                      data rate
 */
struct data_rate_settings_t {
	ssize_t num_data_rate_settings;
	struct data_rate_reg_info_t data_rate_settings[MAX_DATA_RATES];
};

/**
 * struct csiphy_ctrl_t
 * @csiphy_reg: Register address
@@ -161,6 +187,9 @@ struct csiphy_device;
 * @getclockvoting: function pointer which
 *      is used to find the clock voting
 *      for the sensor output data rate
 * @data_rate_settings_table:
 *      Table which maintains the resgister
 *      settings specific to data rate
 */
struct csiphy_ctrl_t {
	struct csiphy_reg_parms_t csiphy_reg;
@@ -172,6 +201,7 @@ struct csiphy_ctrl_t {
	struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];
	struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE];
	enum   cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev);
	struct data_rate_settings_t *data_rates_settings_table;
};

/**
+7 −0
Original line number Diff line number Diff line
@@ -228,6 +228,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
		csiphy_dev->hw_version = CSIPHY_VERSION_V10;
		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;
		csiphy_dev->clk_lane = 0;
		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
	} else if (of_device_is_compatible(soc_info->dev->of_node,
		"qcom,csiphy-v1.1")) {
		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_1_reg;
@@ -246,6 +247,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;
		csiphy_dev->hw_version = CSIPHY_VERSION_V11;
		csiphy_dev->clk_lane = 0;
		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
	} else if (of_device_is_compatible(soc_info->dev->of_node,
		"qcom,csiphy-v1.2")) {
		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg;
@@ -263,6 +265,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW_12;
		csiphy_dev->hw_version = CSIPHY_VERSION_V12;
		csiphy_dev->clk_lane = 0;
		csiphy_dev->ctrl_reg->data_rates_settings_table =
			&data_rate_delta_table;
	} else if (of_device_is_compatible(soc_info->dev->of_node,
		"qcom,csiphy-v1.2.1")) {
		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_1_reg;
@@ -280,6 +284,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW_12;
		csiphy_dev->hw_version = CSIPHY_VERSION_V121;
		csiphy_dev->clk_lane = 0;
		csiphy_dev->ctrl_reg->data_rates_settings_table =
			&data_rate_delta_table_1_2_1;
	} else if (of_device_is_compatible(soc_info->dev->of_node,
		"qcom,csiphy-v2.0")) {
		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg;
@@ -295,6 +301,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
		csiphy_dev->hw_version = CSIPHY_VERSION_V20;
		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;
		csiphy_dev->clk_lane = 0;
		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
	} else {
		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",
			csiphy_dev->hw_version);
+87 −0
Original line number Diff line number Diff line
@@ -410,4 +410,91 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
	},
};

struct data_rate_settings_t data_rate_delta_table_1_2_1 = {
	.num_data_rate_settings = 3,
	.data_rate_settings = {
		{
			/* (2.5 * 10**3 * 2.28) rounded value*/
			.bandwidth = 5700000000,
			.data_rate_reg_array_size = 12,
			.csiphy_data_rate_regs = {
				{0x15C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x35C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x55C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x16C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x36C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x56C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},
			}
		},
		{
			/* (3.5 * 10**3 * 2.28) rounded value */
			.bandwidth = 7980000000,
			.data_rate_reg_array_size = 24,
			.csiphy_data_rate_regs = {
				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
			},
		},
		{
			/* (4.5 * 10**3 * 2.28) rounded value */
			.bandwidth = 10260000000,
			.data_rate_reg_array_size = 24,
			.csiphy_data_rate_regs = {
				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
			},
		}
	}
};

#endif /* _CAM_CSIPHY_1_2_1_HWREG_H_ */
+87 −1
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
 */

#ifndef _CAM_CSIPHY_1_2_HWREG_H_
@@ -389,4 +389,90 @@ csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
	},
};

struct data_rate_settings_t data_rate_delta_table = {
	.num_data_rate_settings = 3,
	.data_rate_settings = {
		{
			/* (2.5 * 10**3 * 2.28) rounded value*/
			.bandwidth = 5700000000,
			.data_rate_reg_array_size = 12,
			.csiphy_data_rate_regs = {
				{0x15C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x35C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x55C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x16C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x36C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x56C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS},
			}
		},
		{
			/* (3.5 * 10**3 * 2.28) rounded value */
			.bandwidth = 7980000000,
			.data_rate_reg_array_size = 24,
			.csiphy_data_rate_regs = {
				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
			},
		},
		{
			/* (4.5 * 10**3 * 2.28) rounded value */
			.bandwidth = 10260000000,
			.data_rate_reg_array_size = 24,
			.csiphy_data_rate_regs = {
				{0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
				{0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
			},
		}
	}
};
#endif /* _CAM_CSIPHY_1_2_HWREG_H_ */