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Commit 80f43c7f authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: npu: Initialize status registers and ipc before fw boots up"

parents 1cb39385 feb27637

arch/arm64/boot/dts/qcom/kona-npu.dtsi

+22 −88
Original line number Diff line number Diff line
@@ -41,17 +41,13 @@ 
				<&clock_npucc NPU_CC_DPM_TEMP_CLK>,

				<&clock_npucc NPU_CC_CAL_HM0_DPM_IP_CLK>,

				<&clock_npucc NPU_CC_CAL_HM1_DPM_IP_CLK>,

				<&clock_npucc NPU_CC_DSP_AHBS_CLK>,

				<&clock_npucc NPU_CC_DSP_AHBM_CLK>,

				<&clock_npucc NPU_CC_DSP_AXI_CLK>,

				<&clock_npucc NPU_CC_DSP_BWMON_CLK>,

				<&clock_npucc NPU_CC_DSP_BWMON_AHB_CLK>,

				<&clock_npucc NPU_CC_ATB_CLK>,

				<&clock_npucc NPU_CC_S2P_CLK>,

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_CAL_HM1_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>;

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_DSP_CORE_CLK_SRC>;

		clock-names = "xo_clk",

				"npu_core_clk",

				"cal_hm0_clk",
@@ -74,17 +70,13 @@ 
				"dpm_temp_clk",

				"cal_hm0_dpm_ip_clk",

				"cal_hm1_dpm_ip_clk",

				"dsp_ahbs_clk",

				"dsp_ahbm_clk",

				"dsp_axi_clk",

				"dsp_bwmon_clk",

				"dsp_bwmon_ahb_clk",

				"atb_clk",

				"s2p_clk",

				"bwmon_clk",

				"cal_hm0_perf_cnt_clk",

				"cal_hm1_perf_cnt_clk",

				"bto_core_clk";

				"bto_core_clk",

				"dsp_core_clk_src";



		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -98,44 +90,6 @@ 
			initial-pwrlevel = <4>;

			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <0>;

				clk-freq = <19200000

					60000000

					200000000

					200000000

					200000000

					200000000

					120000000

					20000000

					200000000

					60000000

					19200000

					50000000

					50000000

					60000000

					60000000

					60000000

					19200000

					60000000

					19200000

					50000000

					200000000

					200000000

					60000000

					60000000

					120000000

					19200000

					60000000

					30000000

					50000000

					19200000

					200000000

					200000000

					19200000>;

			};



			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <1>;

				clk-freq = <19200000

					100000000
@@ -159,21 +113,17 @@ 
					50000000

					200000000

					200000000

					100000000

					100000000

					200000000

					19200000

					100000000

					60000000

					50000000

					19200000

					300000000

					300000000

					19200000>;

					19200000

					300000000>;

			};



			qcom,npu-pwrlevel@2 {

				reg = <2>;

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <2>;

				clk-freq = <19200000

					200000000
@@ -197,21 +147,17 @@ 
					50000000

					466000000

					466000000

					200000000

					200000000

					267000000

					19200000

					200000000

					120000000

					50000000

					19200000

					466000000

					466000000

					19200000>;

					19200000

					400000000>;

			};



			qcom,npu-pwrlevel@3 {

				reg = <3>;

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				vreg = <3>;

				clk-freq = <19200000

					333000000
@@ -235,21 +181,17 @@ 
					50000000

					533000000

					533000000

					333000000

					333000000

					403000000

					19200000

					333000000

					240000000

					50000000

					19200000

					533000000

					533000000

					19200000>;

					19200000

					500000000>;

			};



			qcom,npu-pwrlevel@4 {

				reg = <4>;

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				vreg = <4>;

				clk-freq = <19200000

					428000000
@@ -273,21 +215,17 @@ 
					100000000

					850000000

					850000000

					428000000

					428000000

					533000000

					19200000

					428000000

					240000000

					100000000

					19200000

					850000000

					850000000

					19200000>;

					19200000

					660000000>;

			};



			qcom,npu-pwrlevel@5 {

				reg = <5>;

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <19200000

					500000000
@@ -311,17 +249,13 @@ 
					100000000

					1000000000

					1000000000

					500000000

					500000000

					700000000

					19200000

					500000000

					30000000

					100000000

					19200000

					1000000000

					1000000000

					19200000>;

					19200000

					800000000>;

			};

		};

	};

drivers/media/platform/msm/npu/npu_dev.c

+36 −8
Original line number Diff line number Diff line
@@ -586,7 +586,7 @@ static int npu_enable_clocks(struct npu_device *npu_dev, bool post_pil) 


static void npu_disable_clocks(struct npu_device *npu_dev, bool post_pil)

{

	int i = 0;

	int i, rc = 0;

	struct npu_clk *core_clks = npu_dev->core_clks;



	for (i = npu_dev->core_clk_num - 1; i >= 0 ; i--) {
@@ -598,6 +598,18 @@ static void npu_disable_clocks(struct npu_device *npu_dev, bool post_pil) 
				continue;

		}



		/* set clock rate to 0 before disabling it */

		if (!npu_is_exclude_rate_clock(core_clks[i].clk_name)) {

			pr_debug("setting rate of clock %s to 0\n",

				core_clks[i].clk_name);



			rc = clk_set_rate(core_clks[i].clk, 0);

			if (rc) {

				pr_err("clk_set_rate %s to 0 failed\n",

					core_clks[i].clk_name);

			}

		}



		pr_debug("disabling clock %s\n", core_clks[i].clk_name);

		clk_disable_unprepare(core_clks[i].clk);

	}
@@ -744,13 +756,29 @@ int npu_enable_sys_cache(struct npu_device *npu_dev) 
		}



		/* set npu side regs - program SCID */

		reg_val = NPU_CACHE_ATTR_IDn___POR | SYS_CACHE_SCID;



		REGW(npu_dev, NPU_CACHE_ATTR_IDn(0), reg_val);

		REGW(npu_dev, NPU_CACHE_ATTR_IDn(1), reg_val);

		REGW(npu_dev, NPU_CACHE_ATTR_IDn(2), reg_val);

		REGW(npu_dev, NPU_CACHE_ATTR_IDn(3), reg_val);

		REGW(npu_dev, NPU_CACHE_ATTR_IDn(4), reg_val);

		reg_val = REGR(npu_dev, NPU_CACHEMAP0_ATTR_IDn(0));

		reg_val = (reg_val & ~NPU_CACHEMAP_SCID_MASK) | SYS_CACHE_SCID;



		REGW(npu_dev, NPU_CACHEMAP0_ATTR_IDn(0), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_IDn(1), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_IDn(2), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_IDn(3), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_IDn(4), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_METADATA_IDn(0), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_METADATA_IDn(1), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_METADATA_IDn(2), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_METADATA_IDn(3), reg_val);

		REGW(npu_dev, NPU_CACHEMAP0_ATTR_METADATA_IDn(4), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_IDn(0), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_IDn(1), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_IDn(2), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_IDn(3), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_IDn(4), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_METADATA_IDn(0), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_METADATA_IDn(1), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_METADATA_IDn(2), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_METADATA_IDn(3), reg_val);

		REGW(npu_dev, NPU_CACHEMAP1_ATTR_METADATA_IDn(4), reg_val);



		pr_debug("prior to activate sys cache\n");

		rc = llcc_slice_activate(npu_dev->sys_cache);

drivers/media/platform/msm/npu/npu_hw.h

+5 −2
Original line number Diff line number Diff line
@@ -12,8 +12,11 @@ 
 */

#define NPU_HW_VERSION (0x00000000)

#define NPU_MASTERn_IPC_IRQ_OUT(n) (0x00001004+0x1000*(n))

#define NPU_CACHE_ATTR_IDn___POR 0x00011100

#define NPU_CACHE_ATTR_IDn(n) (0x00000800+0x4*(n))

#define NPU_CACHEMAP0_ATTR_IDn(n) (0x00000800+0x4*(n))

#define NPU_CACHEMAP0_ATTR_METADATA_IDn(n) (0x00000814+0x4*(n))

#define NPU_CACHEMAP1_ATTR_IDn(n) (0x00000830+0x4*(n))

#define NPU_CACHEMAP1_ATTR_METADATA_IDn(n) (0x00000844+0x4*(n))

#define NPU_CACHEMAP_SCID_MASK 0x0000001F

#define NPU_MASTERn_IPC_IRQ_IN_CTRL(n) (0x00001008+0x1000*(n))

#define NPU_MASTER0_IPC_IRQ_IN_CTRL__IRQ_SOURCE_SELECT___S 4

#define NPU_MASTERn_IPC_IRQ_OUT_CTRL(n) (0x00001004+0x1000*(n))

drivers/media/platform/msm/npu/npu_mgr.c

+21 −28
Original line number Diff line number Diff line
@@ -88,14 +88,6 @@ int fw_init(struct npu_device *npu_dev) 
		goto enable_sys_cache_fail;

	}



	/* Boot the NPU subsystem */

	host_ctx->subsystem_handle = subsystem_get_local("npu");

	if (IS_ERR(host_ctx->subsystem_handle)) {

		pr_err("pil load npu fw failed\n");

		ret = -ENODEV;

		goto subsystem_get_fail;

	}



	/* Clear control/status registers */

	REGW(npu_dev, REG_NPU_FW_CTRL_STATUS, 0x0);

	REGW(npu_dev, REG_NPU_HOST_CTRL_VALUE, 0x0);
@@ -109,31 +101,31 @@ int fw_init(struct npu_device *npu_dev) 
	if (host_ctx->fw_dbg_mode & FW_DBG_DISABLE_WDOG)

		reg_val |= HOST_CTRL_STATUS_DISABLE_WDOG_VAL;



	/* Enable clock gating only if the HW access platform allows it */

	if (npu_hw_clk_gating_enabled())

		reg_val |= HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_VAL;



	REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);

	/* Read back to flush all registers for fw to read */

	REGR(npu_dev, REG_NPU_HOST_CTRL_STATUS);



	/* Initialize the host side IPC before fw boots up */

	npu_host_ipc_pre_init(npu_dev);



	/* Boot the NPU subsystem */

	host_ctx->subsystem_handle = subsystem_get_local("npu");

	if (IS_ERR(host_ctx->subsystem_handle)) {

		pr_err("pil load npu fw failed\n");

		ret = -ENODEV;

		goto subsystem_get_fail;

	}



	/* Post PIL clocks */

	if (npu_enable_post_pil_clocks(npu_dev)) {

		ret = -EPERM;

		goto enable_post_clk_fail;

	}



	/*

	 * Set logging state and clock gating state

	 * during FW bootup initialization

	 */

	reg_val = REGR(npu_dev, REG_NPU_HOST_CTRL_STATUS);



	/* Enable clock gating only if the HW access platform allows it */

	if (npu_hw_clk_gating_enabled())

		reg_val |= HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_VAL;



	REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);



	/* Initialize the host side IPC */

	npu_host_ipc_pre_init(npu_dev);



	/* Keep reading ctrl status until NPU is ready */

	pr_debug("waiting for status ready from fw\n");
@@ -170,11 +162,12 @@ int fw_init(struct npu_device *npu_dev) 
wait_fw_ready_fail:

	npu_disable_post_pil_clocks(npu_dev);

enable_post_clk_fail:

	subsystem_put_local(host_ctx->subsystem_handle);

subsystem_get_fail:

	npu_disable_sys_cache(npu_dev);

enable_sys_cache_fail:

	npu_disable_sys_cache(npu_dev);

	npu_disable_core_power(npu_dev);

	if (!IS_ERR(host_ctx->subsystem_handle))

		subsystem_put_local(host_ctx->subsystem_handle);

enable_pw_fail:

	host_ctx->fw_state = FW_DISABLED;

	mutex_unlock(&host_ctx->lock);
@@ -236,8 +229,6 @@ void fw_deinit(struct npu_device *npu_dev, bool ssr, bool fw_alive) 


	npu_disable_post_pil_clocks(npu_dev);

	npu_disable_sys_cache(npu_dev);

	subsystem_put_local(host_ctx->subsystem_handle);

	host_ctx->fw_state = FW_DISABLED;



	/*

	 * if fw is still alive, notify dsp before power off
@@ -251,6 +242,9 @@ void fw_deinit(struct npu_device *npu_dev, bool ssr, bool fw_alive) 


	npu_disable_core_power(npu_dev);



	subsystem_put_local(host_ctx->subsystem_handle);

	host_ctx->fw_state = FW_DISABLED;



	if (ssr) {

		/* mark all existing network to error state */

		for (i = 0; i < MAX_LOADED_NETWORK; i++) {
@@ -277,7 +271,6 @@ int npu_host_init(struct npu_device *npu_dev) 
	mutex_init(&host_ctx->lock);

	atomic_set(&host_ctx->ipc_trans_id, 1);



	host_ctx->sys_cache_disable = true;

	host_ctx->wq = npu_create_wq(host_ctx, "irq_hdl", host_irq_wq,

		&host_ctx->irq_work);

	if (!host_ctx->wq)