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Commit feb27637 authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Initialize status registers and ipc before fw boots up 



Status registers and ipc queue are used for communication between
fw and host driver need to be cleared before fw is loaded via PIL.

Change-Id: I32351621709985a733caece8622e195155e5ed2e
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 0e321cd5

drivers/media/platform/msm/npu/npu_mgr.c

+15 −23
Original line number Diff line number Diff line
@@ -88,14 +88,6 @@ int fw_init(struct npu_device *npu_dev) 
		goto enable_sys_cache_fail;

	}



	/* Boot the NPU subsystem */

	host_ctx->subsystem_handle = subsystem_get_local("npu");

	if (IS_ERR(host_ctx->subsystem_handle)) {

		pr_err("pil load npu fw failed\n");

		ret = -ENODEV;

		goto subsystem_get_fail;

	}



	/* Clear control/status registers */

	REGW(npu_dev, REG_NPU_FW_CTRL_STATUS, 0x0);

	REGW(npu_dev, REG_NPU_HOST_CTRL_VALUE, 0x0);
@@ -109,31 +101,31 @@ int fw_init(struct npu_device *npu_dev) 
	if (host_ctx->fw_dbg_mode & FW_DBG_DISABLE_WDOG)

		reg_val |= HOST_CTRL_STATUS_DISABLE_WDOG_VAL;



	/* Enable clock gating only if the HW access platform allows it */

	if (npu_hw_clk_gating_enabled())

		reg_val |= HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_VAL;



	REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);

	/* Read back to flush all registers for fw to read */

	REGR(npu_dev, REG_NPU_HOST_CTRL_STATUS);



	/* Initialize the host side IPC before fw boots up */

	npu_host_ipc_pre_init(npu_dev);



	/* Boot the NPU subsystem */

	host_ctx->subsystem_handle = subsystem_get_local("npu");

	if (IS_ERR(host_ctx->subsystem_handle)) {

		pr_err("pil load npu fw failed\n");

		ret = -ENODEV;

		goto subsystem_get_fail;

	}



	/* Post PIL clocks */

	if (npu_enable_post_pil_clocks(npu_dev)) {

		ret = -EPERM;

		goto enable_post_clk_fail;

	}



	/*

	 * Set logging state and clock gating state

	 * during FW bootup initialization

	 */

	reg_val = REGR(npu_dev, REG_NPU_HOST_CTRL_STATUS);



	/* Enable clock gating only if the HW access platform allows it */

	if (npu_hw_clk_gating_enabled())

		reg_val |= HOST_CTRL_STATUS_BOOT_ENABLE_CLK_GATE_VAL;



	REGW(npu_dev, REG_NPU_HOST_CTRL_STATUS, reg_val);



	/* Initialize the host side IPC */

	npu_host_ipc_pre_init(npu_dev);



	/* Keep reading ctrl status until NPU is ready */

	pr_debug("waiting for status ready from fw\n");