Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7c9422ef authored by Chanwoo Choi's avatar Chanwoo Choi Committed by Kukjin Kim
Browse files

clk: exynos3250: Add cpu clock configuration data and instaniate cpu clock 



This patch add CPU clock configuration data and instantiate the CPU
clock type for Exynos3250 to support Samsung specific cpu-clock type.

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Acked-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: default avatarMichael Turquette <mturquette@baylibre.com>
Signed-off-by: default avatarKukjin Kim <kgene@kernel.org>
parent d7cc4c81

drivers/clk/samsung/clk-exynos3250.c

+30 −2
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <dt-bindings/clock/exynos3250.h>



#include "clk.h"

#include "clk-cpu.h"

#include "clk-pll.h"



#define SRC_LEFTBUS		0x4200
@@ -319,8 +320,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = { 
	MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,

	    SRC_CPU, 24, 1),

	MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),

	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),

	MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),

	MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,

			CLK_SET_RATE_PARENT, 0),

	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,

			CLK_SET_RATE_PARENT, 0),

};



static struct samsung_div_clock div_clks[] __initdata = {
@@ -772,6 +775,26 @@ static struct samsung_cmu_info cmu_info __initdata = { 
	.nr_clk_regs		= ARRAY_SIZE(exynos3250_cmu_clk_regs),

};



#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem)			\

		(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\

		((corem) << 4))

#define E3250_CPU_DIV1(hpm, copy)					\

		(((hpm) << 4) | ((copy) << 0))



static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {

	{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },

	{  900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },

	{  100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },

	{  0 },

};



static void __init exynos3250_cmu_init(struct device_node *np)

{

	struct samsung_clk_provider *ctx;
@@ -780,6 +803,11 @@ static void __init exynos3250_cmu_init(struct device_node *np) 
	if (!ctx)

		return;



	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_core_p[0], mout_core_p[1], 0x14200,

			e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),

			CLK_CPU_HAS_DIV1);



	exynos3_core_down_clock(ctx->reg_base);

}

CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);

include/dt-bindings/clock/exynos3250.h

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define CLK_FOUT_VPLL			4

#define CLK_FOUT_UPLL			5

#define CLK_FOUT_MPLL			6

#define CLK_ARM_CLK			7



/* Muxes */

#define CLK_MOUT_MPLL_USER_L		16