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Commit d7cc4c81 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
Browse files

clk: exynos5250: add cpu clock configuration data and instantiate cpu clock 



With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5250.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
[b.zolnierkie: split exynos5250 support from the original patch]
[b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c]
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: default avatarJavier Martinez Canillas <javier@dowhile0.org>
Tested-by: default avatarJavier Martinez Canillas <javier@dowhile0.org>
Acked-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarMichael Turquette <mturquette@baylibre.com>
Signed-off-by: default avatarKukjin Kim <kgene@kernel.org>
parent d770e558

drivers/clk/samsung/clk-exynos5250.c

+31 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <linux/syscore_ops.h>



#include "clk.h"

#include "clk-cpu.h"



#define APLL_LOCK		0x0

#define APLL_CON0		0x100
@@ -748,6 +749,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 
		VPLL_LOCK, VPLL_CON0, NULL),

};



#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud)		\

		((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\

		 ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))

#define E5250_CPU_DIV1(hpm, copy)					\

		(((hpm) << 4) | (copy))



static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {

	{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },

	{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },

	{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },

	{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },

	{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },

	{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },

	{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },

	{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },

	{  0 },

};



static const struct of_device_id ext_clk_match[] __initconst = {

	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },

	{ },
@@ -797,6 +824,10 @@ static void __init exynos5250_clk_init(struct device_node *np) 
			ARRAY_SIZE(exynos5250_div_clks));

	samsung_clk_register_gate(ctx, exynos5250_gate_clks,

			ARRAY_SIZE(exynos5250_gate_clks));

	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_cpu_p[0], mout_cpu_p[1], 0x200,

			exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),

			CLK_CPU_HAS_DIV1);



	/*

	 * Enable arm clock down (in idle) and set arm divider

include/dt-bindings/clock/exynos5250.h

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define CLK_FOUT_CPLL		6

#define CLK_FOUT_EPLL		7

#define CLK_FOUT_VPLL		8

#define CLK_ARM_CLK		9



/* gate for special clocks (sclk) */

#define CLK_SCLK_CAM_BAYER	128