Loading qcom/bengal-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -1289,6 +1289,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; coresight-ctis = <&cti0>; coresight-csr = <&csr>; ports { #address-cells = <1>; #size-cells = <0>; Loading Loading
qcom/bengal-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -1289,6 +1289,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; coresight-ctis = <&cti0>; coresight-csr = <&csr>; ports { #address-cells = <1>; #size-cells = <0>; Loading