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Commit dd987915 authored May 06, 2021 by Jagadeesh Kona

dt-bindings: clock: Add support for KHAJE clock controllers

Update the GCC, GPUCC, DISPCC and debug clock controller
bindings for KHAJE device.

Change-Id: I1272755c6943c490078f23965f122b3f4e63ffba

parent a81e78a7

bindings/clock/qcom,debugcc.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,7 @@ Required properties :
		"qcom,sdm660-debugcc" "qcom,sdm429w-debugcc"
		"qcom,msm8937-debugcc" "qcom,msm8917-debugcc"
		"qcom,sdm429w-debugcc", "qcom,qm215-debugcc"
		or "qcom,sdm450-debugcc".
		or "qcom,sdm450-debugcc", "qcom,khaje-debugcc".
		- qcom,gcc: phandle to the GCC device node.
		- qcom,videocc: phandle to the Video CC device node.
		- qcom,camcc: phandle to the Camera CC device node.

bindings/clock/qcom,dispcc.txt

+2 −1

Original line number	Diff line number	Diff line
		@@ -9,7 +9,8 @@ Required properties :
		"qcom,lito-dispcc"
		"qcom,bengal-dispcc"
		"qcom,lagoon-dispcc"
		"qcom,scuba-dispcc".
		"qcom,scuba-dispcc"
		"qcom,khaje-dispcc".
		- reg : shall contain base register location and length.
		- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf
		of the clocks.

bindings/clock/qcom,gcc.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,7 @@ Required properties :
		"qcom,gcc-mdss-qm215"
		"qcom,gcc-mdss-sdm429w"
		"qcom,gcc-mdss-sdm439"
		"qcom,khaje-gcc"

		- reg : shall contain base register location and length
		- #clock-cells : shall contain 1

bindings/clock/qcom,gpucc.txt

+2 −1

Original line number	Diff line number	Diff line
		@@ -9,7 +9,8 @@ Required properties :
		"qcom,lagoon-gpucc",
		"qcom,gpu-sdm660",
		"qcom,gpucc-sdm660",
		"qcom,gpucc-sdm630".
		"qcom,gpucc-sdm630",
		"qcom,khaje-gpucc".

		- reg: shall contain base register offset and size.
		- reg-names: names of registers listed in the same order as in the reg property.