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Commit 7a816233 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "i2c-qcom-geni: Add I2C GENI driver snapshot"

parents 446cb9ae 1e6a82eb

Documentation/devicetree/bindings/i2c/qcom,i2c-qcom-geni.txt

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GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)

								I2C controller



Required properties:

 - compatible: Should be:

   * "qcom,i2c-geni.

 - reg: Should contain QUP register address and length.

 - interrupts: Should contain I2C interrupt.

 - clocks: Serial engine core clock, and AHB clocks needed by the device.

 - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names

   should be "active" and "sleep" for the pin confuguration when core is active

   or when entering sleep state.

 - #address-cells: Should be <1> Address cells for i2c device address

 - #size-cells: Should be <0> as i2c addresses have no size component

 - qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.



Optional property:

 - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.

   When missing default to 400000Hz.



Child nodes should conform to i2c bus binding.



Example:



i2c@a94000 {

	compatible = "qcom,i2c-geni";

	reg = <0xa94000 0x4000>;

	interrupts = <GIC_SPI 358 0>;

	clock-names = "se-clk", "m-ahb", "s-ahb";

	clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&qup_1_i2c_5_active>;

	pinctrl-1 = <&qup_1_i2c_5_sleep>;

	#address-cells = <1>;

	#size-cells = <0>;

	qcom,wrapper-core = <&qupv3_0>;

	qcom,clk-freq-out = <400000>;

};

arch/arm64/boot/dts/qcom/kona.dtsi

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@@ -2477,6 +2477,59 @@ 
			qcom,dump-id = <0x127>;

		};

	};



	gpi_dma0: qcom,gpi-dma@900000 {

		#dma-cells = <5>;

		compatible = "qcom,gpi-dma";

		reg = <0x900000 0x70000>;

		reg-names = "gpi-top";

		interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,

			     <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,

			     <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,

			     <0 256 0>;

		qcom,max-num-gpii = <13>;

		qcom,gpii-mask = <0x7ff>;

		qcom,ev-factor = <2>;

		iommus = <&apps_smmu 0x5b6 0x0>;

		qcom,smmu-cfg = <0x1>;

		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

		status = "ok";

	};



	gpi_dma1: qcom,gpi-dma@a00000 {

		#dma-cells = <5>;

		compatible = "qcom,gpi-dma";

		reg = <0xa00000 0x70000>;

		reg-names = "gpi-top";

		interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>,

			     <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>,

			     <0 295 0>, <0 296 0>;

		qcom,max-num-gpii = <10>;

		qcom,gpii-mask = <0x3f>;

		qcom,ev-factor = <2>;

		iommus = <&apps_smmu 0x56 0x0>;

		qcom,smmu-cfg = <0x1>;

		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

		status = "ok";

	};



	gpi_dma2: qcom,gpi-dma@800000 {

		#dma-cells = <5>;

		compatible = "qcom,gpi-dma";

		reg = <0x800000 0x70000>;

		reg-names = "gpi-top";

		interrupts = <0 588 0>, <0 589 0>, <0 590 0>, <0 591 0>,

			     <0 592 0>, <0 593 0>, <0 594 0>, <0 595 0>,

			     <0 596 0>, <0 597 0>;

		qcom,max-num-gpii = <10>;

		qcom,gpii-mask = <0x3f>;

		qcom,ev-factor = <2>;

		iommus = <&apps_smmu 0x76 0x0>;

		qcom,smmu-cfg = <0x1>;

		qcom,iova-range = <0x0 0x100000 0x0 0x100000>;

		status = "ok";

	};



};



#include "kona-regulators.dtsi"

drivers/dma/qcom/Kconfig

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@@ -27,3 +27,22 @@ config QCOM_HIDMA 
	  (user to kernel, kernel to kernel, etc.).  It only supports

	  memcpy interface. The core is not intended for general

	  purpose slave DMA.



config QCOM_GPI_DMA

        tristate "Qualcomm Technologies Inc GPI DMA support"

        depends on ARCH_QCOM

        select DMA_ENGINE

        select DMA_VIRTUAL_CHANNELS

        help

          Enable support for the QCOM GPI DMA controller. This controller

          provides DMA capabilities for a variety of peripheral buses such

          as I2C, UART, and SPI. By using GPI dmaengine driver, bus drivers

          can use a standardize interface that is protocol independent to

          transfer data between DDR and peripheral.



config QCOM_GPI_DMA_DEBUG

	bool "Qualcomm Technologies Inc GPI debug support"

	depends on QCOM_GPI_DMA

	help

	  Enable detailed logging for QCOM GPI driver. Extra logging will be

	  helpful when debugging critical issues.

drivers/dma/qcom/Makefile

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@@ -4,3 +4,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o 
hdma_mgmt-objs	 := hidma_mgmt.o hidma_mgmt_sys.o

obj-$(CONFIG_QCOM_HIDMA) +=  hdma.o

hdma-objs        := hidma_ll.o hidma.o hidma_dbg.o

obj-$(CONFIG_QCOM_GPI_DMA) += gpi.o

drivers/dma/qcom/gpi.c

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