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Commit 77835952 authored by Lynus Vaz's avatar Lynus Vaz Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Use common CX_MISC functions for GPU LLC setup 



The CX_MISC registers are used to configure the GPU LLC settings. Use
the common CX_MISC access functions now that we have this block set
up.

Change-Id: Ie2528e1a85452ac553401be527bc9350feefea34
Signed-off-by: default avatarLynus Vaz <lvaz@codeaurora.org>
parent fb8e863f

drivers/gpu/msm/a6xx_reg.h

+11 −0
Original line number Diff line number Diff line
@@ -1105,5 +1105,16 @@ 
#define A6XX_RGMU_CX_PCC_STATUS			0x1F83C

#define A6XX_RGMU_CX_PCC_DEBUG			0x1F83D



/* GPU CX_MISC registers */

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0	0x1

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1	0x2

#define A6XX_LLC_NUM_GPU_SCIDS			5

#define A6XX_GPU_LLC_SCID_NUM_BITS		5

#define A6XX_GPU_LLC_SCID_MASK \

	((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)

#define A6XX_GPUHTW_LLC_SCID_SHIFT		25

#define A6XX_GPUHTW_LLC_SCID_MASK \

	(((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)



#endif /* _A6XX_REG_H */

drivers/gpu/msm/adreno_a6xx.c

+7 −48
Original line number Diff line number Diff line
@@ -24,18 +24,6 @@ 


#define MIN_HBB		13



#define A6XX_LLC_NUM_GPU_SCIDS		5

#define A6XX_GPU_LLC_SCID_NUM_BITS	5

#define A6XX_GPU_LLC_SCID_MASK \

	((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1)

#define A6XX_GPUHTW_LLC_SCID_SHIFT	25

#define A6XX_GPUHTW_LLC_SCID_MASK \

	(((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT)



#define A6XX_GPU_CX_REG_BASE		0x509E000

#define A6XX_GPU_CX_REG_SIZE		0x1000





static const struct adreno_vbif_data a630_vbif[] = {

	{A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009},

	{A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3},
@@ -1582,24 +1570,6 @@ static void a6xx_err_callback(struct adreno_device *adreno_dev, int bit) 
	}

}



/* GPU System Cache control registers */

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0   0x4

#define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1   0x8



static inline void _reg_rmw(void __iomem *regaddr,

	unsigned int mask, unsigned int bits)

{

	unsigned int val = 0;



	val = __raw_readl(regaddr);

	/* Make sure the above read completes before we proceed  */

	rmb();

	val &= ~mask;

	__raw_writel(val | bits, regaddr);

	/* Make sure the above write posts before we proceed*/

	wmb();

}



/*

 * a6xx_llc_configure_gpu_scid() - Program the sub-cache ID for all GPU blocks

 * @adreno_dev: The adreno device pointer
@@ -1619,13 +1589,9 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
		kgsl_regrmw(KGSL_DEVICE(adreno_dev), A6XX_GBIF_SCACHE_CNTL1,

			A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

	} else {

		void __iomem *gpu_cx_reg;



		gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE,

			A6XX_GPU_CX_REG_SIZE);

		_reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

		adreno_cx_misc_regrmw(adreno_dev,

				A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

				A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val);

		iounmap(gpu_cx_reg);

	}

}
@@ -1636,7 +1602,6 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) 
static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev)

{

	uint32_t gpuhtw_scid;

	void __iomem *gpu_cx_reg;



	/*

	 * On A640, the GPUHTW SCID is configured via a NoC override in the
@@ -1647,11 +1612,10 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) 


	gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice);



	gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE);

	_reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

	adreno_cx_misc_regrmw(adreno_dev,

			A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1,

			A6XX_GPUHTW_LLC_SCID_MASK,

			gpuhtw_scid << A6XX_GPUHTW_LLC_SCID_SHIFT);

	iounmap(gpu_cx_reg);

}



/*
@@ -1660,8 +1624,6 @@ static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) 
 */

static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev)

{

	void __iomem *gpu_cx_reg;



	/*

	 * Attributes override through GBIF is not supported with MMU-500.

	 * Attributes are used as configured through SMMU pagetable entries.
@@ -1675,11 +1637,8 @@ static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) 
	 *      writenoallocoverrideen=1

	 *      write-no-alloc=1 - Do not allocates lines on write miss

	 */

	gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE);

	__raw_writel(0x3, gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0);

	/* Make sure the above write posts before we proceed*/

	wmb();

	iounmap(gpu_cx_reg);

	adreno_cx_misc_regwrite(adreno_dev,

			A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0, 0x3);

}



static const char *fault_block[8] = {