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Commit 74860cbf authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'exynos-drm-next-for-v4.18-v2' of... 

Merge tag 'exynos-drm-next-for-v4.18-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos

 into drm-next

Add more HW overlays support
- It enables hardware overlay number 4 and 5. For this,
  this patch series adds required clocks.

Several fixups
- Fix default value of zpos according to real hardware overlay number.
- Fix error value of exynos_Drm_crtc_get_by_type function correctly.
- Fix static checker warning of scaler_task_done function.
- Fix signedness bug in fimc_setup_clocks function.

One cleanup
- Disable framedone interrupt of DSI device which is not required.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1527229919-25665-1-git-send-email-inki.dae@samsung.com
parents dd41fb85 19832055

Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt

+7 −2
Original line number Diff line number Diff line
@@ -19,7 +19,8 @@ Required properties: 
	  clock-names property.

- clock-names: list of clock names sorted in the same order as the clocks

	       property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",

	       "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",

	       "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",

	       "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",

	       "sclk_decon_eclk"

- ports: contains a port which is connected to mic node. address-cells and

	 size-cells must 1 and 0, respectively.
@@ -34,10 +35,14 @@ decon: decon@13800000 { 
	clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,

		<&cmu_disp CLK_ACLK_XIU_DECON0X>,

		<&cmu_disp CLK_PCLK_SMMU_DECON0X>,

		<&cmu_disp CLK_ACLK_SMMU_DECON1X>,

		<&cmu_disp CLK_ACLK_XIU_DECON1X>,

		<&cmu_disp CLK_PCLK_SMMU_DECON1X>,

		<&cmu_disp CLK_SCLK_DECON_VCLK>,

		<&cmu_disp CLK_SCLK_DECON_ECLK>;

	clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",

		"pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk";

		"pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",

		"pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";

	interrupt-names = "vsync", "lcd_sys";

	interrupts = <0 202 0>, <0 203 0>;

drivers/gpu/drm/exynos/exynos5433_drm_decon.c

+12 −9
Original line number Diff line number Diff line
@@ -31,7 +31,10 @@ 
#define DSD_CFG_MUX 0x1004

#define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)



#define WINDOWS_NR	3

#define WINDOWS_NR	5

#define PRIMARY_WIN	2

#define CURSON_WIN	4



#define MIN_FB_WIDTH_FOR_16WORD_BURST	128



#define I80_HW_TRG	(1 << 0)
@@ -43,6 +46,9 @@ static const char * const decon_clks_name[] = { 
	"aclk_smmu_decon0x",

	"aclk_xiu_decon0x",

	"pclk_smmu_decon0x",

	"aclk_smmu_decon1x",

	"aclk_xiu_decon1x",

	"pclk_smmu_decon1x",

	"sclk_decon_vclk",

	"sclk_decon_eclk",

};
@@ -74,9 +80,8 @@ static const uint32_t decon_formats[] = { 
};



static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {

	DRM_PLANE_TYPE_PRIMARY,

	DRM_PLANE_TYPE_OVERLAY,

	DRM_PLANE_TYPE_CURSOR,

	[PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,

	[CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,

};



static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
@@ -552,12 +557,10 @@ static int decon_bind(struct device *dev, struct device *master, void *data) 
	drm_dev->max_vblank_count = 0xffffffff;



	for (win = ctx->first_win; win < WINDOWS_NR; win++) {

		int tmp = (win == ctx->first_win) ? 0 : win;



		ctx->configs[win].pixel_formats = decon_formats;

		ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);

		ctx->configs[win].zpos = win;

		ctx->configs[win].type = decon_win_types[tmp];

		ctx->configs[win].zpos = win - ctx->first_win;

		ctx->configs[win].type = decon_win_types[win];



		ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,

					&ctx->configs[win]);
@@ -565,7 +568,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) 
			return ret;

	}



	exynos_plane = &ctx->planes[ctx->first_win];

	exynos_plane = &ctx->planes[PRIMARY_WIN];

	out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI

						  : EXYNOS_DISPLAY_TYPE_LCD;

	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,

drivers/gpu/drm/exynos/exynos_drm_crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ struct exynos_drm_crtc *exynos_drm_crtc_get_by_type(struct drm_device *drm_dev, 
		if (to_exynos_crtc(crtc)->type == out_type)

			return to_exynos_crtc(crtc);



	return ERR_PTR(-EPERM);

	return ERR_PTR(-ENODEV);

}



int exynos_drm_set_possible_crtcs(struct drm_encoder *encoder,

drivers/gpu/drm/exynos/exynos_drm_dsi.c

+3 −3
Original line number Diff line number Diff line
@@ -1264,15 +1264,15 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 


	if (status & DSIM_INT_SW_RST_RELEASE) {

		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |

			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE |

			DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE);

			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |

			DSIM_INT_SW_RST_RELEASE);

		exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);

		complete(&dsi->completed);

		return IRQ_HANDLED;

	}



	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |

			DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE)))

			DSIM_INT_PLL_STABLE)))

		return IRQ_HANDLED;



	if (exynos_dsi_transfer_finish(dsi))

drivers/gpu/drm/exynos/exynos_drm_fimc.c

+1 −1
Original line number Diff line number Diff line
@@ -1200,7 +1200,7 @@ static int fimc_setup_clocks(struct fimc_context *ctx) 


int exynos_drm_check_fimc_device(struct device *dev)

{

	unsigned int id = of_alias_get_id(dev->of_node, "fimc");

	int id = of_alias_get_id(dev->of_node, "fimc");



	if (id >= 0 && (BIT(id) & fimc_mask))

		return 0;