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Commit 728f288d authored by Stephen Boyd's avatar Stephen Boyd
Browse files

clk: samsung: Remove CLK_IS_ROOT 



This flag is a no-op now. Remove usage of the flag.

Acked-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 2c63935d

drivers/clk/samsung/clk-exynos4.c

+6 −6
Original line number Diff line number Diff line
@@ -500,19 +500,19 @@ PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none", 


/* fixed rate clocks generated outside the soc */

static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {

	FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0),

	FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0),

	FRATE(CLK_XXTI, "xxti", NULL, 0, 0),

	FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),

};



/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {

	FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),

	FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),

	FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),

};



static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {

	FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),

	FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),

};



static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {
@@ -1251,7 +1251,7 @@ static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) 
	fclk.id = CLK_FIN_PLL;

	fclk.name = "fin_pll";

	fclk.parent_name = NULL;

	fclk.flags = CLK_IS_ROOT;

	fclk.flags = 0;

	fclk.fixed_rate = finpll_f;

	samsung_clk_register_fixed_rate(ctx, &fclk, 1);

drivers/clk/samsung/clk-exynos4415.c

+1 −1
Original line number Diff line number Diff line
@@ -274,7 +274,7 @@ static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initda 
};



static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),

};



static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {

drivers/clk/samsung/clk-exynos5250.c

+5 −5
Original line number Diff line number Diff line
@@ -262,15 +262,15 @@ PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 


/* fixed rate clocks generated outside the soc */

static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {

	FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),

	FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),

};



/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),

	FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),

	FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),

	FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),

	FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),

};



static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {

drivers/clk/samsung/clk-exynos5260.c

+16 −20
Original line number Diff line number Diff line
@@ -1432,42 +1432,38 @@ static unsigned long top_clk_regs[] __initdata = { 
/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {

	FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,

			CLK_IS_ROOT, 270000000),

			0, 270000000),

	FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,

			CLK_IS_ROOT, 270000000),

			0, 270000000),

	FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,

			CLK_IS_ROOT, 270000000),

			0, 270000000),

	FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,

			CLK_IS_ROOT, 270000000),

			0, 270000000),

	FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,

			CLK_IS_ROOT, 250000000),

			0, 250000000),

	FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,

			CLK_IS_ROOT, 1660000000),

			0, 1660000000),

	FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",

			NULL, CLK_IS_ROOT, 125000000),

			NULL, 0, 125000000),

	FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,

			"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,

			CLK_IS_ROOT, 187500000),

			0, 187500000),

	FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",

			NULL, CLK_IS_ROOT, 24000000),

			NULL, 0, 24000000),

	FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,

			CLK_IS_ROOT, 135000000),

			0, 135000000),

	FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,

			"phyclk_mipi_dphy_4l_m_rxclkesc0", NULL,

			CLK_IS_ROOT, 20000000),

			"phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),

	FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",

			NULL, CLK_IS_ROOT, 60000000),

			NULL, 0, 60000000),

	FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",

			NULL, CLK_IS_ROOT, 60000000),

			NULL, 0, 60000000),

	FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,

			"phyclk_usbhost20_phy_clk48mohci",

			NULL, CLK_IS_ROOT, 48000000),

			"phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),

	FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,

			"phyclk_usbdrd30_udrd30_pipe_pclk", NULL,

			CLK_IS_ROOT, 125000000),

			"phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),

	FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,

			"phyclk_usbdrd30_udrd30_phyclock", NULL,

			CLK_IS_ROOT, 60000000),

			"phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),

};



PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};

drivers/clk/samsung/clk-exynos5420.c

+6 −6
Original line number Diff line number Diff line
@@ -480,16 +480,16 @@ PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 
/* fixed rate clocks generated outside the soc */

static struct samsung_fixed_rate_clock

		exynos5x_fixed_rate_ext_clks[] __initdata = {

	FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),

	FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),

};



/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),

	FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),

	FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),

	FRATE(0, "sclk_pwi", NULL, 0, 24000000),

	FRATE(0, "sclk_usbh20", NULL, 0, 48000000),

	FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),

	FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),

};



static struct samsung_fixed_factor_clock