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Commit 7259f645 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ntb-4.18' of git://github.com/jonmason/ntb 

Pull NTB updates from Jon Mason:

 - reorg and clean-up of the Intel NTB driver

 - a trivial comment change

 - change GFP_ATOMIC to GFP_KERNEL where appropriate

* tag 'ntb-4.18' of git://github.com/jonmason/ntb:
  ntb: ntb_transport: Replace GFP_ATOMIC with GFP_KERNEL in ntb_transport_create_queue
  ntb: ntb_transport: Replace GFP_ATOMIC with GFP_KERNEL in ntb_transport_setup_qp_mw
  NTB: ntb_hw_idt: fix typo 'can by' to 'can be'
  ntb: intel: change references of skx to gen3
  ntb: intel: split out the gen3 code
  ntb: intel: header definitions refactor
parents 467590e0 c9160b69

drivers/ntb/hw/idt/ntb_hw_idt.c

+1 −1
Original line number Diff line number Diff line
@@ -1401,7 +1401,7 @@ static int idt_ntb_peer_mw_clear_trans(struct ntb_dev *ntb, int pidx, 
 *                          5. Doorbell operations

 *

 *    Doorbell functionality of IDT PCIe-switches is pretty unusual. First of

 * all there is global doorbell register which state can by changed by any

 * all there is global doorbell register which state can be changed by any

 * NT-function of the IDT device in accordance with global permissions. These

 * permissions configs are not supported by NTB API, so it must be done by

 * either BIOS or EEPROM settings. In the same way the state of the global

drivers/ntb/hw/intel/Makefile

+1 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_NTB_INTEL) += ntb_hw_intel.o

ntb_hw_intel-y := ntb_hw_gen1.o ntb_hw_gen3.o

drivers/ntb/hw/intel/ntb_hw_intel.c→drivers/ntb/hw/intel/ntb_hw_gen1.c

+46 −667

File changed and moved.

Preview size limit exceeded, changes collapsed.

drivers/ntb/hw/intel/ntb_hw_gen1.h

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+182 −0
Original line number Diff line number Diff line 
/*

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 *   redistributing this file, you may do so under either license.

 *

 *   GPL LICENSE SUMMARY

 *

 *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.

 *

 *   This program is free software; you can redistribute it and/or modify

 *   it under the terms of version 2 of the GNU General Public License as

 *   published by the Free Software Foundation.

 *

 *   BSD LICENSE

 *

 *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.

 *

 *   Redistribution and use in source and binary forms, with or without

 *   modification, are permitted provided that the following conditions

 *   are met:

 *

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copy

 *       notice, this list of conditions and the following disclaimer in

 *       the documentation and/or other materials provided with the

 *       distribution.

 *     * Neither the name of Intel Corporation nor the names of its

 *       contributors may be used to endorse or promote products derived

 *       from this software without specific prior written permission.

 *

 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef _NTB_INTEL_GEN1_H_

#define _NTB_INTEL_GEN1_H_



#include "ntb_hw_intel.h"



/* Intel Gen1 Xeon hardware */

#define XEON_PBAR23LMT_OFFSET		0x0000

#define XEON_PBAR45LMT_OFFSET		0x0008

#define XEON_PBAR4LMT_OFFSET		0x0008

#define XEON_PBAR5LMT_OFFSET		0x000c

#define XEON_PBAR23XLAT_OFFSET		0x0010

#define XEON_PBAR45XLAT_OFFSET		0x0018

#define XEON_PBAR4XLAT_OFFSET		0x0018

#define XEON_PBAR5XLAT_OFFSET		0x001c

#define XEON_SBAR23LMT_OFFSET		0x0020

#define XEON_SBAR45LMT_OFFSET		0x0028

#define XEON_SBAR4LMT_OFFSET		0x0028

#define XEON_SBAR5LMT_OFFSET		0x002c

#define XEON_SBAR23XLAT_OFFSET		0x0030

#define XEON_SBAR45XLAT_OFFSET		0x0038

#define XEON_SBAR4XLAT_OFFSET		0x0038

#define XEON_SBAR5XLAT_OFFSET		0x003c

#define XEON_SBAR0BASE_OFFSET		0x0040

#define XEON_SBAR23BASE_OFFSET		0x0048

#define XEON_SBAR45BASE_OFFSET		0x0050

#define XEON_SBAR4BASE_OFFSET		0x0050

#define XEON_SBAR5BASE_OFFSET		0x0054

#define XEON_SBDF_OFFSET		0x005c

#define XEON_NTBCNTL_OFFSET		0x0058

#define XEON_PDOORBELL_OFFSET		0x0060

#define XEON_PDBMSK_OFFSET		0x0062

#define XEON_SDOORBELL_OFFSET		0x0064

#define XEON_SDBMSK_OFFSET		0x0066

#define XEON_USMEMMISS_OFFSET		0x0070

#define XEON_SPAD_OFFSET		0x0080

#define XEON_PBAR23SZ_OFFSET		0x00d0

#define XEON_PBAR45SZ_OFFSET		0x00d1

#define XEON_PBAR4SZ_OFFSET		0x00d1

#define XEON_SBAR23SZ_OFFSET		0x00d2

#define XEON_SBAR45SZ_OFFSET		0x00d3

#define XEON_SBAR4SZ_OFFSET		0x00d3

#define XEON_PPD_OFFSET			0x00d4

#define XEON_PBAR5SZ_OFFSET		0x00d5

#define XEON_SBAR5SZ_OFFSET		0x00d6

#define XEON_WCCNTRL_OFFSET		0x00e0

#define XEON_UNCERRSTS_OFFSET		0x014c

#define XEON_CORERRSTS_OFFSET		0x0158

#define XEON_LINK_STATUS_OFFSET		0x01a2

#define XEON_SPCICMD_OFFSET		0x0504

#define XEON_DEVCTRL_OFFSET		0x0598

#define XEON_DEVSTS_OFFSET		0x059a

#define XEON_SLINK_STATUS_OFFSET	0x05a2

#define XEON_B2B_SPAD_OFFSET		0x0100

#define XEON_B2B_DOORBELL_OFFSET	0x0140

#define XEON_B2B_XLAT_OFFSETL		0x0144

#define XEON_B2B_XLAT_OFFSETU		0x0148

#define XEON_PPD_CONN_MASK		0x03

#define XEON_PPD_CONN_TRANSPARENT	0x00

#define XEON_PPD_CONN_B2B		0x01

#define XEON_PPD_CONN_RP		0x02

#define XEON_PPD_DEV_MASK		0x10

#define XEON_PPD_DEV_USD		0x00

#define XEON_PPD_DEV_DSD		0x10

#define XEON_PPD_SPLIT_BAR_MASK		0x40



#define XEON_PPD_TOPO_MASK	(XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)

#define XEON_PPD_TOPO_PRI_USD	(XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)

#define XEON_PPD_TOPO_PRI_DSD	(XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)

#define XEON_PPD_TOPO_SEC_USD	(XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)

#define XEON_PPD_TOPO_SEC_DSD	(XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)

#define XEON_PPD_TOPO_B2B_USD	(XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)

#define XEON_PPD_TOPO_B2B_DSD	(XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)



#define XEON_MW_COUNT			2

#define HSX_SPLIT_BAR_MW_COUNT		3

#define XEON_DB_COUNT			15

#define XEON_DB_LINK			15

#define XEON_DB_LINK_BIT			BIT_ULL(XEON_DB_LINK)

#define XEON_DB_MSIX_VECTOR_COUNT	4

#define XEON_DB_MSIX_VECTOR_SHIFT	5

#define XEON_DB_TOTAL_SHIFT		16

#define XEON_SPAD_COUNT			16



/* Use the following addresses for translation between b2b ntb devices in case

 * the hardware default values are not reliable. */

#define XEON_B2B_BAR0_ADDR	0x1000000000000000ull

#define XEON_B2B_BAR2_ADDR64	0x2000000000000000ull

#define XEON_B2B_BAR4_ADDR64	0x4000000000000000ull

#define XEON_B2B_BAR4_ADDR32	0x20000000u

#define XEON_B2B_BAR5_ADDR32	0x40000000u



/* The peer ntb secondary config space is 32KB fixed size */

#define XEON_B2B_MIN_SIZE		0x8000



/* flags to indicate hardware errata */

#define NTB_HWERR_SDOORBELL_LOCKUP	BIT_ULL(0)

#define NTB_HWERR_SB01BASE_LOCKUP	BIT_ULL(1)

#define NTB_HWERR_B2BDOORBELL_BIT14	BIT_ULL(2)

#define NTB_HWERR_MSIX_VECTOR32_BAD	BIT_ULL(3)



extern struct intel_b2b_addr xeon_b2b_usd_addr;

extern struct intel_b2b_addr xeon_b2b_dsd_addr;



int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max,

		int msix_shift, int total_shift);

enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);

u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio);

int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,

				void __iomem *mmio);

int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx);

int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx);

int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,

		resource_size_t *addr_align, resource_size_t *size_align,

		resource_size_t *size_max);

int intel_ntb_peer_mw_count(struct ntb_dev *ntb);

int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx,

		phys_addr_t *base, resource_size_t *size);

u64 intel_ntb_link_is_up(struct ntb_dev *ntb, enum ntb_speed *speed,

		enum ntb_width *width);

int intel_ntb_link_disable(struct ntb_dev *ntb);

u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb);

int intel_ntb_db_vector_count(struct ntb_dev *ntb);

u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector);

int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits);

int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits);

int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,

		resource_size_t *db_size);

int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb);

int intel_ntb_spad_count(struct ntb_dev *ntb);

u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx);

int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val);

u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx);

int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, int sidx,

		u32 val);

int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx,

				    phys_addr_t *spad_addr);

int xeon_link_is_up(struct intel_ntb_dev *ndev);



#endif

drivers/ntb/hw/intel/ntb_hw_gen3.c

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+597 −0
Original line number Diff line number Diff line 
/*

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 *   redistributing this file, you may do so under either license.

 *

 *   GPL LICENSE SUMMARY

 *

 *   Copyright(c) 2017 Intel Corporation. All rights reserved.

 *

 *   This program is free software; you can redistribute it and/or modify

 *   it under the terms of version 2 of the GNU General Public License as

 *   published by the Free Software Foundation.

 *

 *   BSD LICENSE

 *

 *   Copyright(c) 2017 Intel Corporation. All rights reserved.

 *

 *   Redistribution and use in source and binary forms, with or without

 *   modification, are permitted provided that the following conditions

 *   are met:

 *

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copy

 *       notice, this list of conditions and the following disclaimer in

 *       the documentation and/or other materials provided with the

 *       distribution.

 *     * Neither the name of Intel Corporation nor the names of its

 *       contributors may be used to endorse or promote products derived

 *       from this software without specific prior written permission.

 *

 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 *

 * Intel PCIe GEN3 NTB Linux driver

 *

 */



#include <linux/debugfs.h>

#include <linux/delay.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/pci.h>

#include <linux/random.h>

#include <linux/slab.h>

#include <linux/ntb.h>



#include "ntb_hw_intel.h"

#include "ntb_hw_gen1.h"

#include "ntb_hw_gen3.h"



static int gen3_poll_link(struct intel_ntb_dev *ndev);



static const struct intel_ntb_reg gen3_reg = {

	.poll_link		= gen3_poll_link,

	.link_is_up		= xeon_link_is_up,

	.db_ioread		= gen3_db_ioread,

	.db_iowrite		= gen3_db_iowrite,

	.db_size		= sizeof(u32),

	.ntb_ctl		= GEN3_NTBCNTL_OFFSET,

	.mw_bar			= {2, 4},

};



static const struct intel_ntb_alt_reg gen3_pri_reg = {

	.db_bell		= GEN3_EM_DOORBELL_OFFSET,

	.db_clear		= GEN3_IM_INT_STATUS_OFFSET,

	.db_mask		= GEN3_IM_INT_DISABLE_OFFSET,

	.spad			= GEN3_IM_SPAD_OFFSET,

};



static const struct intel_ntb_alt_reg gen3_b2b_reg = {

	.db_bell		= GEN3_IM_DOORBELL_OFFSET,

	.db_clear		= GEN3_EM_INT_STATUS_OFFSET,

	.db_mask		= GEN3_EM_INT_DISABLE_OFFSET,

	.spad			= GEN3_B2B_SPAD_OFFSET,

};



static const struct intel_ntb_xlat_reg gen3_sec_xlat = {

/*	.bar0_base		= GEN3_EMBAR0_OFFSET, */

	.bar2_limit		= GEN3_IMBAR1XLMT_OFFSET,

	.bar2_xlat		= GEN3_IMBAR1XBASE_OFFSET,

};



static int gen3_poll_link(struct intel_ntb_dev *ndev)

{

	u16 reg_val;

	int rc;



	ndev->reg->db_iowrite(ndev->db_link_mask,

			      ndev->self_mmio +

			      ndev->self_reg->db_clear);



	rc = pci_read_config_word(ndev->ntb.pdev,

				  GEN3_LINK_STATUS_OFFSET, &reg_val);

	if (rc)

		return 0;



	if (reg_val == ndev->lnk_sta)

		return 0;



	ndev->lnk_sta = reg_val;



	return 1;

}



static int gen3_init_isr(struct intel_ntb_dev *ndev)

{

	int i;



	/*

	 * The MSIX vectors and the interrupt status bits are not lined up

	 * on Skylake. By default the link status bit is bit 32, however it

	 * is by default MSIX vector0. We need to fixup to line them up.

	 * The vectors at reset is 1-32,0. We need to reprogram to 0-32.

	 */



	for (i = 0; i < GEN3_DB_MSIX_VECTOR_COUNT; i++)

		iowrite8(i, ndev->self_mmio + GEN3_INTVEC_OFFSET + i);



	/* move link status down one as workaround */

	if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) {

		iowrite8(GEN3_DB_MSIX_VECTOR_COUNT - 2,

			 ndev->self_mmio + GEN3_INTVEC_OFFSET +

			 (GEN3_DB_MSIX_VECTOR_COUNT - 1));

	}



	return ndev_init_isr(ndev, GEN3_DB_MSIX_VECTOR_COUNT,

			     GEN3_DB_MSIX_VECTOR_COUNT,

			     GEN3_DB_MSIX_VECTOR_SHIFT,

			     GEN3_DB_TOTAL_SHIFT);

}



static int gen3_setup_b2b_mw(struct intel_ntb_dev *ndev,

			    const struct intel_b2b_addr *addr,

			    const struct intel_b2b_addr *peer_addr)

{

	struct pci_dev *pdev;

	void __iomem *mmio;

	phys_addr_t bar_addr;



	pdev = ndev->ntb.pdev;

	mmio = ndev->self_mmio;



	/* setup incoming bar limits == base addrs (zero length windows) */

	bar_addr = addr->bar2_addr64;

	iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET);

	bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);

	dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);



	bar_addr = addr->bar4_addr64;

	iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET);

	bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);

	dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);



	/* zero incoming translation addrs */

	iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET);

	iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET);



	ndev->peer_mmio = ndev->self_mmio;



	return 0;

}



static int gen3_init_ntb(struct intel_ntb_dev *ndev)

{

	int rc;





	ndev->mw_count = XEON_MW_COUNT;

	ndev->spad_count = GEN3_SPAD_COUNT;

	ndev->db_count = GEN3_DB_COUNT;

	ndev->db_link_mask = GEN3_DB_LINK_BIT;



	/* DB fixup for using 31 right now */

	if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)

		ndev->db_link_mask |= BIT_ULL(31);



	switch (ndev->ntb.topo) {

	case NTB_TOPO_B2B_USD:

	case NTB_TOPO_B2B_DSD:

		ndev->self_reg = &gen3_pri_reg;

		ndev->peer_reg = &gen3_b2b_reg;

		ndev->xlat_reg = &gen3_sec_xlat;



		if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {

			rc = gen3_setup_b2b_mw(ndev,

					      &xeon_b2b_dsd_addr,

					      &xeon_b2b_usd_addr);

		} else {

			rc = gen3_setup_b2b_mw(ndev,

					      &xeon_b2b_usd_addr,

					      &xeon_b2b_dsd_addr);

		}



		if (rc)

			return rc;



		/* Enable Bus Master and Memory Space on the secondary side */

		iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,

			  ndev->self_mmio + GEN3_SPCICMD_OFFSET);



		break;



	default:

		return -EINVAL;

	}



	ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;



	ndev->reg->db_iowrite(ndev->db_valid_mask,

			      ndev->self_mmio +

			      ndev->self_reg->db_mask);



	return 0;

}



int gen3_init_dev(struct intel_ntb_dev *ndev)

{

	struct pci_dev *pdev;

	u8 ppd;

	int rc;



	pdev = ndev->ntb.pdev;



	ndev->reg = &gen3_reg;



	rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);

	if (rc)

		return -EIO;



	ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);

	dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,

		ntb_topo_string(ndev->ntb.topo));

	if (ndev->ntb.topo == NTB_TOPO_NONE)

		return -EINVAL;



	ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;



	rc = gen3_init_ntb(ndev);

	if (rc)

		return rc;



	return gen3_init_isr(ndev);

}



ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,

				      size_t count, loff_t *offp)

{

	struct intel_ntb_dev *ndev;

	void __iomem *mmio;

	char *buf;

	size_t buf_size;

	ssize_t ret, off;

	union { u64 v64; u32 v32; u16 v16; } u;



	ndev = filp->private_data;

	mmio = ndev->self_mmio;



	buf_size = min(count, 0x800ul);



	buf = kmalloc(buf_size, GFP_KERNEL);

	if (!buf)

		return -ENOMEM;



	off = 0;



	off += scnprintf(buf + off, buf_size - off,

			 "NTB Device Information:\n");



	off += scnprintf(buf + off, buf_size - off,

			 "Connection Topology -\t%s\n",

			 ntb_topo_string(ndev->ntb.topo));



	off += scnprintf(buf + off, buf_size - off,

			 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);

	off += scnprintf(buf + off, buf_size - off,

			 "LNK STA -\t\t%#06x\n", ndev->lnk_sta);



	if (!ndev->reg->link_is_up(ndev))

		off += scnprintf(buf + off, buf_size - off,

				 "Link Status -\t\tDown\n");

	else {

		off += scnprintf(buf + off, buf_size - off,

				 "Link Status -\t\tUp\n");

		off += scnprintf(buf + off, buf_size - off,

				 "Link Speed -\t\tPCI-E Gen %u\n",

				 NTB_LNK_STA_SPEED(ndev->lnk_sta));

		off += scnprintf(buf + off, buf_size - off,

				 "Link Width -\t\tx%u\n",

				 NTB_LNK_STA_WIDTH(ndev->lnk_sta));

	}



	off += scnprintf(buf + off, buf_size - off,

			 "Memory Window Count -\t%u\n", ndev->mw_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Scratchpad Count -\t%u\n", ndev->spad_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Count -\t%u\n", ndev->db_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);



	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);



	u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Mask -\t\t%#llx\n", u.v64);



	u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Bell -\t\t%#llx\n", u.v64);



	off += scnprintf(buf + off, buf_size - off,

			 "\nNTB Incoming XLAT:\n");



	u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR1XBASE -\t\t%#018llx\n", u.v64);



	u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR2XBASE -\t\t%#018llx\n", u.v64);



	u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR1XLMT -\t\t\t%#018llx\n", u.v64);



	u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR2XLMT -\t\t\t%#018llx\n", u.v64);



	if (ntb_topo_is_b2b(ndev->ntb.topo)) {

		off += scnprintf(buf + off, buf_size - off,

				 "\nNTB Outgoing B2B XLAT:\n");



		u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR1XBASE -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR2XBASE -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR1XLMT -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR2XLMT -\t\t%#018llx\n", u.v64);



		off += scnprintf(buf + off, buf_size - off,

				 "\nNTB Secondary BAR:\n");



		u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR0 -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR1 -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR2 -\t\t%#018llx\n", u.v64);

	}



	off += scnprintf(buf + off, buf_size - off,

			 "\nNTB Statistics:\n");



	u.v16 = ioread16(mmio + GEN3_USMEMMISS_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "Upstream Memory Miss -\t%u\n", u.v16);



	off += scnprintf(buf + off, buf_size - off,

			 "\nNTB Hardware Errors:\n");



	if (!pci_read_config_word(ndev->ntb.pdev,

				  GEN3_DEVSTS_OFFSET, &u.v16))

		off += scnprintf(buf + off, buf_size - off,

				 "DEVSTS -\t\t%#06x\n", u.v16);



	if (!pci_read_config_word(ndev->ntb.pdev,

				  GEN3_LINK_STATUS_OFFSET, &u.v16))

		off += scnprintf(buf + off, buf_size - off,

				 "LNKSTS -\t\t%#06x\n", u.v16);



	if (!pci_read_config_dword(ndev->ntb.pdev,

				   GEN3_UNCERRSTS_OFFSET, &u.v32))

		off += scnprintf(buf + off, buf_size - off,

				 "UNCERRSTS -\t\t%#06x\n", u.v32);



	if (!pci_read_config_dword(ndev->ntb.pdev,

				   GEN3_CORERRSTS_OFFSET, &u.v32))

		off += scnprintf(buf + off, buf_size - off,

				 "CORERRSTS -\t\t%#06x\n", u.v32);



	ret = simple_read_from_buffer(ubuf, count, offp, buf, off);

	kfree(buf);

	return ret;

}



static int intel_ntb3_link_enable(struct ntb_dev *ntb,

				  enum ntb_speed max_speed,

				  enum ntb_width max_width)

{

	struct intel_ntb_dev *ndev;

	u32 ntb_ctl;



	ndev = container_of(ntb, struct intel_ntb_dev, ntb);



	dev_dbg(&ntb->pdev->dev,

		"Enabling link with max_speed %d max_width %d\n",

		max_speed, max_width);



	if (max_speed != NTB_SPEED_AUTO)

		dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);

	if (max_width != NTB_WIDTH_AUTO)

		dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);



	ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);

	ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);

	ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;

	ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;

	iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);



	return 0;

}

static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,

				   dma_addr_t addr, resource_size_t size)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);

	unsigned long xlat_reg, limit_reg;

	resource_size_t bar_size, mw_size;

	void __iomem *mmio;

	u64 base, limit, reg_val;

	int bar;



	if (pidx != NTB_DEF_PEER_IDX)

		return -EINVAL;



	if (idx >= ndev->b2b_idx && !ndev->b2b_off)

		idx += 1;



	bar = ndev_mw_to_bar(ndev, idx);

	if (bar < 0)

		return bar;



	bar_size = pci_resource_len(ndev->ntb.pdev, bar);



	if (idx == ndev->b2b_idx)

		mw_size = bar_size - ndev->b2b_off;

	else

		mw_size = bar_size;



	/* hardware requires that addr is aligned to bar size */

	if (addr & (bar_size - 1))

		return -EINVAL;



	/* make sure the range fits in the usable mw size */

	if (size > mw_size)

		return -EINVAL;



	mmio = ndev->self_mmio;

	xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);

	limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);

	base = pci_resource_start(ndev->ntb.pdev, bar);



	/* Set the limit if supported, if size is not mw_size */

	if (limit_reg && size != mw_size)

		limit = base + size;

	else

		limit = base + mw_size;



	/* set and verify setting the translation address */

	iowrite64(addr, mmio + xlat_reg);

	reg_val = ioread64(mmio + xlat_reg);

	if (reg_val != addr) {

		iowrite64(0, mmio + xlat_reg);

		return -EIO;

	}



	dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);



	/* set and verify setting the limit */

	iowrite64(limit, mmio + limit_reg);

	reg_val = ioread64(mmio + limit_reg);

	if (reg_val != limit) {

		iowrite64(base, mmio + limit_reg);

		iowrite64(0, mmio + xlat_reg);

		return -EIO;

	}



	dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);



	/* setup the EP */

	limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;

	base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx));

	base &= ~0xf;



	if (limit_reg && size != mw_size)

		limit = base + size;

	else

		limit = base + mw_size;



	/* set and verify setting the limit */

	iowrite64(limit, mmio + limit_reg);

	reg_val = ioread64(mmio + limit_reg);

	if (reg_val != limit) {

		iowrite64(base, mmio + limit_reg);

		iowrite64(0, mmio + xlat_reg);

		return -EIO;

	}



	dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);



	return 0;

}



static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);

	int bit;



	if (db_bits & ~ndev->db_valid_mask)

		return -EINVAL;



	while (db_bits) {

		bit = __ffs(db_bits);

		iowrite32(1, ndev->peer_mmio +

				ndev->peer_reg->db_bell + (bit * 4));

		db_bits &= db_bits - 1;

	}



	return 0;

}



static u64 intel_ntb3_db_read(struct ntb_dev *ntb)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);



	return ndev_db_read(ndev,

			    ndev->self_mmio +

			    ndev->self_reg->db_clear);

}



static int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);



	return ndev_db_write(ndev, db_bits,

			     ndev->self_mmio +

			     ndev->self_reg->db_clear);

}



const struct ntb_dev_ops intel_ntb3_ops = {

	.mw_count		= intel_ntb_mw_count,

	.mw_get_align		= intel_ntb_mw_get_align,

	.mw_set_trans		= intel_ntb3_mw_set_trans,

	.peer_mw_count		= intel_ntb_peer_mw_count,

	.peer_mw_get_addr	= intel_ntb_peer_mw_get_addr,

	.link_is_up		= intel_ntb_link_is_up,

	.link_enable		= intel_ntb3_link_enable,

	.link_disable		= intel_ntb_link_disable,

	.db_valid_mask		= intel_ntb_db_valid_mask,

	.db_vector_count	= intel_ntb_db_vector_count,

	.db_vector_mask		= intel_ntb_db_vector_mask,

	.db_read		= intel_ntb3_db_read,

	.db_clear		= intel_ntb3_db_clear,

	.db_set_mask		= intel_ntb_db_set_mask,

	.db_clear_mask		= intel_ntb_db_clear_mask,

	.peer_db_addr		= intel_ntb_peer_db_addr,

	.peer_db_set		= intel_ntb3_peer_db_set,

	.spad_is_unsafe		= intel_ntb_spad_is_unsafe,

	.spad_count		= intel_ntb_spad_count,

	.spad_read		= intel_ntb_spad_read,

	.spad_write		= intel_ntb_spad_write,

	.peer_spad_addr		= intel_ntb_peer_spad_addr,

	.peer_spad_read		= intel_ntb_peer_spad_read,

	.peer_spad_write	= intel_ntb_peer_spad_write,

};