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Commit 6fd5a295 authored by Pawan Gupta's avatar Pawan Gupta Committed by Greg Kroah-Hartman
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x86/tsx: Add a feature bit for TSX control MSR support 



commit aaa65d17eec372c6a9756833f3964ba05b05ea14 upstream.

Support for the TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES.
This is different from how other CPU features are enumerated i.e. via
CPUID. Currently, a call to tsx_ctrl_is_supported() is required for
enumerating the feature. In the absence of a feature bit for TSX control,
any code that relies on checking feature bits directly will not work.

In preparation for adding a feature bit check in MSR save/restore
during suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when
MSR_IA32_TSX_CTRL is present.

  [ bp: Remove tsx_ctrl_is_supported()]

  [Pawan: Resolved conflicts in backport; Removed parts of commit message
          referring to removed function tsx_ctrl_is_supported()]

Suggested-by: default avatarAndrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: default avatarPawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/de619764e1d98afbb7a5fa58424f1278ede37b45.1668539735.git.pawan.kumar.gupta@linux.intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4722ac3b

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -292,6 +292,7 @@ 
#define X86_FEATURE_RETPOLINE		(11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_LFENCE	(11*32+13) /* "" Use LFENCE for Spectre variant 2 */

#define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */

#define X86_FEATURE_MSR_TSX_CTRL	(11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

arch/x86/kernel/cpu/tsx.c

+14 −19
Original line number Diff line number Diff line
@@ -55,24 +55,6 @@ void tsx_enable(void) 
	wrmsrl(MSR_IA32_TSX_CTRL, tsx);

}



static bool __init tsx_ctrl_is_supported(void)

{

	u64 ia32_cap = x86_read_arch_cap_msr();



	/*

	 * TSX is controlled via MSR_IA32_TSX_CTRL.  However, support for this

	 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.

	 *

	 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a

	 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES

	 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get

	 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,

	 * tsx= cmdline requests will do nothing on CPUs without

	 * MSR_IA32_TSX_CTRL support.

	 */

	return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);

}



static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)

{

	if (boot_cpu_has_bug(X86_BUG_TAA))
@@ -86,9 +68,22 @@ void __init tsx_init(void) 
	char arg[5] = {};

	int ret;



	if (!tsx_ctrl_is_supported())

	/*

	 * TSX is controlled via MSR_IA32_TSX_CTRL.  However, support for this

	 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.

	 *

	 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a

	 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES

	 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get

	 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,

	 * tsx= cmdline requests will do nothing on CPUs without

	 * MSR_IA32_TSX_CTRL support.

	 */

	if (!(x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR))

		return;



	setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);



	ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));

	if (ret >= 0) {

		if (!strcmp(arg, "on")) {