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Commit 6edc794a authored by Tomasz Figa's avatar Tomasz Figa Committed by Kukjin Kim
Browse files

pinctrl: samsung: Add support for EXYNOS4X12 



This patch extends the driver with any necessary SoC-specific
definitions to support EXYNOS4X12 SoCs.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Acked-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent bab797f8

Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ on-chip controllers onto these pads. 
Required Properties:

- compatible: should be one of the following.

  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.

  - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.

  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.



- reg: Base address of the pin controller hardware module and length of

drivers/pinctrl/pinctrl-exynos.c

+110 −0
Original line number Diff line number Diff line
@@ -566,3 +566,113 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { 
		.label		= "exynos4210-gpio-ctrl2",

	},

};



/* pin banks of exynos4x12 pin-controller 0 */

static struct samsung_pin_bank exynos4x12_pin_banks0[] = {

	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),

	EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),

	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),

	EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),

	EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),

	EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),

	EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),

	EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),

	EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),

	EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),

	EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),

	EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),

	EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),

};



/* pin banks of exynos4x12 pin-controller 1 */

static struct samsung_pin_bank exynos4x12_pin_banks1[] = {

	EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),

	EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),

	EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),

	EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),

	EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),

	EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),

	EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),

	EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),

	EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),

	EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),

	EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),

	EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),

	EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),

	EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),

	EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),

	EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),

	EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),

	EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),

	EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),

	EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),

	EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),

	EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),

	EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),

};



/* pin banks of exynos4x12 pin-controller 2 */

static struct samsung_pin_bank exynos4x12_pin_banks2[] = {

	EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),

};



/* pin banks of exynos4x12 pin-controller 3 */

static struct samsung_pin_bank exynos4x12_pin_banks3[] = {

	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),

	EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),

	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),

	EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),

	EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),

};



/*

 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes

 * four gpio/pin-mux/pinconfig controllers.

 */

struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {

	{

		/* pin-controller instance 0 data */

		.pin_banks	= exynos4x12_pin_banks0,

		.nr_banks	= ARRAY_SIZE(exynos4x12_pin_banks0),

		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,

		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,

		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,

		.svc		= EXYNOS_SVC_OFFSET,

		.eint_gpio_init = exynos_eint_gpio_init,

		.label		= "exynos4x12-gpio-ctrl0",

	}, {

		/* pin-controller instance 1 data */

		.pin_banks	= exynos4x12_pin_banks1,

		.nr_banks	= ARRAY_SIZE(exynos4x12_pin_banks1),

		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,

		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,

		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,

		.weint_con	= EXYNOS_WKUP_ECON_OFFSET,

		.weint_mask	= EXYNOS_WKUP_EMASK_OFFSET,

		.weint_pend	= EXYNOS_WKUP_EPEND_OFFSET,

		.svc		= EXYNOS_SVC_OFFSET,

		.eint_gpio_init = exynos_eint_gpio_init,

		.eint_wkup_init = exynos_eint_wkup_init,

		.label		= "exynos4x12-gpio-ctrl1",

	}, {

		/* pin-controller instance 2 data */

		.pin_banks	= exynos4x12_pin_banks2,

		.nr_banks	= ARRAY_SIZE(exynos4x12_pin_banks2),

		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,

		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,

		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,

		.svc		= EXYNOS_SVC_OFFSET,

		.eint_gpio_init = exynos_eint_gpio_init,

		.label		= "exynos4x12-gpio-ctrl2",

	}, {

		/* pin-controller instance 3 data */

		.pin_banks	= exynos4x12_pin_banks3,

		.nr_banks	= ARRAY_SIZE(exynos4x12_pin_banks3),

		.geint_con	= EXYNOS_GPIO_ECON_OFFSET,

		.geint_mask	= EXYNOS_GPIO_EMASK_OFFSET,

		.geint_pend	= EXYNOS_GPIO_EPEND_OFFSET,

		.svc		= EXYNOS_SVC_OFFSET,

		.eint_gpio_init = exynos_eint_gpio_init,

		.label		= "exynos4x12-gpio-ctrl3",

	},

};

drivers/pinctrl/pinctrl-samsung.c

+2 −0
Original line number Diff line number Diff line
@@ -947,6 +947,8 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev) 
static const struct of_device_id samsung_pinctrl_dt_match[] = {

	{ .compatible = "samsung,pinctrl-exynos4210",

		.data = (void *)exynos4210_pin_ctrl },

	{ .compatible = "samsung,pinctrl-exynos4x12",

		.data = (void *)exynos4x12_pin_ctrl },

	{},

};

MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);

drivers/pinctrl/pinctrl-samsung.h

+1 −0
Original line number Diff line number Diff line
@@ -236,5 +236,6 @@ struct samsung_pmx_func { 


/* list of all exported SoC specific data */

extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];

extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];



#endif /* __PINCTRL_SAMSUNG_H */