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Commit bab797f8 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

Merge remote-tracking branch 'pinctrl/samsung' into next/pinctrl-samsung

parents 3d70f8c6 b33ef91f

Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt

+93 −25
Original line number Diff line number Diff line
@@ -13,8 +13,14 @@ Required Properties: 
- reg: Base address of the pin controller hardware module and length of

  the address space it occupies.



- interrupts: interrupt specifier for the controller. The format and value of

  the interrupt specifier depends on the interrupt parent for the controller.

- Pin banks as child nodes: Pin banks of the controller are represented by child

  nodes of the controller node. Bank name is taken from name of the node. Each

  bank node must contain following properties:



  - gpio-controller: identifies the node as a gpio controller and pin bank.

  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO

    binding is used, the amount of cells must be specified as 2. See generic

    GPIO binding documentation for description of particular cells.



- Pin mux/config groups as child nodes: The pin mux (selecting pin function

  mode) and pin config (pull up/down, driver strength) settings are represented
@@ -72,6 +78,14 @@ used as system wakeup events. 
A. External GPIO Interrupts: For supporting external gpio interrupts, the

   following properties should be specified in the pin-controller device node.



   - interrupt-parent: phandle of the interrupt parent to which the external

     GPIO interrupts are forwarded to.

   - interrupts: interrupt specifier for the controller. The format and value of

     the interrupt specifier depends on the interrupt parent for the controller.



   In addition, following properties must be present in node of every bank

   of pins supporting GPIO interrupts:



   - interrupt-controller: identifies the controller node as interrupt-parent.

   - #interrupt-cells: the value of this property should be 2.

     - First Cell: represents the external gpio interrupt number local to the
@@ -94,6 +108,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 
       found on Samsung Exynos4210 SoC.

   - interrupt-parent: phandle of the interrupt parent to which the external

     wakeup interrupts are forwarded to.

   - interrupts: interrupt used by multiplexed wakeup interrupts.



   In addition, following properties must be present in node of every bank

   of pins supporting wake-up interrupts:



   - interrupt-controller: identifies the node as interrupt-parent.

   - #interrupt-cells: the value of this property should be 2

     - First Cell: represents the external wakeup interrupt number local to
@@ -105,11 +124,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 
       - 4 = high level triggered

       - 8 = low level triggered



   Node of every bank of pins supporting direct wake-up interrupts (without

   multiplexing) must contain following properties:



   - interrupt-parent: phandle of the interrupt parent to which the external

     wakeup interrupts are forwarded to.

   - interrupts: interrupts of the interrupt parent which are used for external

     wakeup interrupts from pins of the bank, must contain interrupts for all

     pins of the bank.



Aliases:



All the pin controller nodes should be represented in the aliases node using

the following format 'pinctrl{n}' where n is a unique number for the alias.



Example: A pin-controller node with pin banks:



	pinctrl_0: pinctrl@11400000 {

		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x11400000 0x1000>;

		interrupts = <0 47 0>;



		/* ... */



		/* Pin bank without external interrupts */

		gpy0: gpy0 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		/* ... */



		/* Pin bank with external GPIO or muxed wake-up interrupts */

		gpj0: gpj0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		/* ... */



		/* Pin bank with external direct wake-up interrupts */

		gpx0: gpx0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			interrupt-parent = <&gic>;

			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,

				     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;

			#interrupt-cells = <2>;

		};



		/* ... */

	};



Example 1: A pin-controller node with pin groups.



	pinctrl_0: pinctrl@11400000 {
@@ -117,6 +188,8 @@ Example 1: A pin-controller node with pin groups. 
		reg = <0x11400000 0x1000>;

		interrupts = <0 47 0>;



		/* ... */



		uart0_data: uart0-data {

			samsung,pins = "gpa0-0", "gpa0-1";

			samsung,pin-function = <2>;
@@ -158,20 +231,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node. 
	pinctrl_1: pinctrl@11000000 {

		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x11000000 0x1000>;

		interrupts = <0 46 0>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <0 46 0>



		wakup_eint: wakeup-interrupt-controller {

		/* ... */



		wakeup-interrupt-controller {

			compatible = "samsung,exynos4210-wakeup-eint";

			interrupt-parent = <&gic>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,

					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,

					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,

					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,

					<0 32 0>;

			interrupts = <0 32 0>;

		};

	};
@@ -190,7 +257,8 @@ Example 4: Set up the default pin state for uart controller. 


	static int s3c24xx_serial_probe(struct platform_device *pdev) {

		struct pinctrl *pinctrl;

		...

		...



		/* ... */



		pinctrl = devm_pinctrl_get_select_default(&pdev->dev);

	}

arch/arm/boot/dts/exynos4210-pinctrl.dtsi

+278 −0
Original line number Diff line number Diff line
@@ -16,6 +16,134 @@ 


/ {

	pinctrl@11400000 {

		gpa0: gpa0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpa1: gpa1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpb: gpb {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpc0: gpc0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpc1: gpc1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpd0: gpd0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpd1: gpd1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpe0: gpe0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpe1: gpe1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpe2: gpe2 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpe3: gpe3 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpe4: gpe4 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpf0: gpf0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpf1: gpf1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpf2: gpf2 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpf3: gpf3 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		uart0_data: uart0-data {

			samsung,pins = "gpa0-0", "gpa0-1";

			samsung,pin-function = <0x2>;
@@ -205,6 +333,151 @@ 
	};



	pinctrl@11000000 {

		gpj0: gpj0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpj1: gpj1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpk0: gpk0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpk1: gpk1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpk2: gpk2 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpk3: gpk3 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpl0: gpl0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpl1: gpl1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpl2: gpl2 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpy0: gpy0 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpy1: gpy1 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpy2: gpy2 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpy3: gpy3 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpy4: gpy4 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpy5: gpy5 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpy6: gpy6 {

			gpio-controller;

			#gpio-cells = <2>;

		};



		gpx0: gpx0 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			interrupt-parent = <&gic>;

			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,

				     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;

			#interrupt-cells = <2>;

		};



		gpx1: gpx1 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			interrupt-parent = <&gic>;

			interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,

				     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;

			#interrupt-cells = <2>;

		};



		gpx2: gpx2 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		gpx3: gpx3 {

			gpio-controller;

			#gpio-cells = <2>;



			interrupt-controller;

			#interrupt-cells = <2>;

		};



		sd0_clk: sd0-clk {

			samsung,pins = "gpk0-0";

			samsung,pin-function = <2>;
@@ -438,6 +711,11 @@ 
	};



	pinctrl@03860000 {

		gpz: gpz {

			gpio-controller;

			#gpio-cells = <2>;

		};



		i2s0_bus: i2s0-bus {

			samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",

					"gpz-4", "gpz-5", "gpz-6";

arch/arm/boot/dts/exynos4210.dtsi

+1 −240
Original line number Diff line number Diff line
@@ -46,27 +46,17 @@ 
		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x11400000 0x1000>;

		interrupts = <0 47 0>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};



	pinctrl_1: pinctrl@11000000 {

		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x11000000 0x1000>;

		interrupts = <0 46 0>;

		interrupt-controller;

		#interrupt-cells = <2>;



		wakup_eint: wakeup-interrupt-controller {

			compatible = "samsung,exynos4210-wakeup-eint";

			interrupt-parent = <&gic>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,

				     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,

				     <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,

				     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,

				     <0 32 0>;

			interrupts = <0 32 0>;

		};

	};
@@ -74,233 +64,4 @@ 
		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x03860000 0x1000>;

	};



	gpio-controllers {

		#address-cells = <1>;

		#size-cells = <1>;

		gpio-controller;

		ranges;



		gpa0: gpio-controller@11400000 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400000 0x20>;

			#gpio-cells = <4>;

		};



		gpa1: gpio-controller@11400020 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400020 0x20>;

			#gpio-cells = <4>;

		};



		gpb: gpio-controller@11400040 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400040 0x20>;

			#gpio-cells = <4>;

		};



		gpc0: gpio-controller@11400060 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400060 0x20>;

			#gpio-cells = <4>;

		};



		gpc1: gpio-controller@11400080 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400080 0x20>;

			#gpio-cells = <4>;

		};



		gpd0: gpio-controller@114000A0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x114000A0 0x20>;

			#gpio-cells = <4>;

		};



		gpd1: gpio-controller@114000C0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x114000C0 0x20>;

			#gpio-cells = <4>;

		};



		gpe0: gpio-controller@114000E0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x114000E0 0x20>;

			#gpio-cells = <4>;

		};



		gpe1: gpio-controller@11400100 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400100 0x20>;

			#gpio-cells = <4>;

		};



		gpe2: gpio-controller@11400120 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400120 0x20>;

			#gpio-cells = <4>;

		};



		gpe3: gpio-controller@11400140 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400140 0x20>;

			#gpio-cells = <4>;

		};



		gpe4: gpio-controller@11400160 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400160 0x20>;

			#gpio-cells = <4>;

		};



		gpf0: gpio-controller@11400180 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11400180 0x20>;

			#gpio-cells = <4>;

		};



		gpf1: gpio-controller@114001A0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x114001A0 0x20>;

			#gpio-cells = <4>;

		};



		gpf2: gpio-controller@114001C0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x114001C0 0x20>;

			#gpio-cells = <4>;

		};



		gpf3: gpio-controller@114001E0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x114001E0 0x20>;

			#gpio-cells = <4>;

		};



		gpj0: gpio-controller@11000000 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000000 0x20>;

			#gpio-cells = <4>;

		};



		gpj1: gpio-controller@11000020 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000020 0x20>;

			#gpio-cells = <4>;

		};



		gpk0: gpio-controller@11000040 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000040 0x20>;

			#gpio-cells = <4>;

		};



		gpk1: gpio-controller@11000060 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000060 0x20>;

			#gpio-cells = <4>;

		};



		gpk2: gpio-controller@11000080 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000080 0x20>;

			#gpio-cells = <4>;

		};



		gpk3: gpio-controller@110000A0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x110000A0 0x20>;

			#gpio-cells = <4>;

		};



		gpl0: gpio-controller@110000C0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x110000C0 0x20>;

			#gpio-cells = <4>;

		};



		gpl1: gpio-controller@110000E0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x110000E0 0x20>;

			#gpio-cells = <4>;

		};



		gpl2: gpio-controller@11000100 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000100 0x20>;

			#gpio-cells = <4>;

		};



		gpy0: gpio-controller@11000120 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000120 0x20>;

			#gpio-cells = <4>;

		};



		gpy1: gpio-controller@11000140 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000140 0x20>;

			#gpio-cells = <4>;

		};



		gpy2: gpio-controller@11000160 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000160 0x20>;

			#gpio-cells = <4>;

		};



		gpy3: gpio-controller@11000180 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000180 0x20>;

			#gpio-cells = <4>;

		};



		gpy4: gpio-controller@110001A0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x110001A0 0x20>;

			#gpio-cells = <4>;

		};



		gpy5: gpio-controller@110001C0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x110001C0 0x20>;

			#gpio-cells = <4>;

		};



		gpy6: gpio-controller@110001E0 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x110001E0 0x20>;

			#gpio-cells = <4>;

		};



		gpx0: gpio-controller@11000C00 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000C00 0x20>;

			#gpio-cells = <4>;

		};



		gpx1: gpio-controller@11000C20 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000C20 0x20>;

			#gpio-cells = <4>;

		};



		gpx2: gpio-controller@11000C40 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000C40 0x20>;

			#gpio-cells = <4>;

		};



		gpx3: gpio-controller@11000C60 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x11000C60 0x20>;

			#gpio-cells = <4>;

		};



		gpz: gpio-controller@03860000 {

			compatible = "samsung,exynos4-gpio";

			reg = <0x03860000 0x20>;

			#gpio-cells = <4>;

		};

	};

};

drivers/pinctrl/pinctrl-exynos.c

+178 −189

File changed.

Preview size limit exceeded, changes collapsed.

drivers/pinctrl/pinctrl-exynos.h

+30 −140
Original line number Diff line number Diff line
@@ -17,125 +17,6 @@ 
 * (at your option) any later version.

 */



#define EXYNOS_GPIO_START(__gpio)	((__gpio##_START) + (__gpio##_NR))



#define EXYNOS4210_GPIO_A0_NR	(8)

#define EXYNOS4210_GPIO_A1_NR	(6)

#define EXYNOS4210_GPIO_B_NR	(8)

#define EXYNOS4210_GPIO_C0_NR	(5)

#define EXYNOS4210_GPIO_C1_NR	(5)

#define EXYNOS4210_GPIO_D0_NR	(4)

#define EXYNOS4210_GPIO_D1_NR	(4)

#define EXYNOS4210_GPIO_E0_NR	(5)

#define EXYNOS4210_GPIO_E1_NR	(8)

#define EXYNOS4210_GPIO_E2_NR	(6)

#define EXYNOS4210_GPIO_E3_NR	(8)

#define EXYNOS4210_GPIO_E4_NR	(8)

#define EXYNOS4210_GPIO_F0_NR	(8)

#define EXYNOS4210_GPIO_F1_NR	(8)

#define EXYNOS4210_GPIO_F2_NR	(8)

#define EXYNOS4210_GPIO_F3_NR	(6)

#define EXYNOS4210_GPIO_J0_NR	(8)

#define EXYNOS4210_GPIO_J1_NR	(5)

#define EXYNOS4210_GPIO_K0_NR	(7)

#define EXYNOS4210_GPIO_K1_NR	(7)

#define EXYNOS4210_GPIO_K2_NR	(7)

#define EXYNOS4210_GPIO_K3_NR	(7)

#define EXYNOS4210_GPIO_L0_NR	(8)

#define EXYNOS4210_GPIO_L1_NR	(3)

#define EXYNOS4210_GPIO_L2_NR	(8)

#define EXYNOS4210_GPIO_Y0_NR	(6)

#define EXYNOS4210_GPIO_Y1_NR	(4)

#define EXYNOS4210_GPIO_Y2_NR	(6)

#define EXYNOS4210_GPIO_Y3_NR	(8)

#define EXYNOS4210_GPIO_Y4_NR	(8)

#define EXYNOS4210_GPIO_Y5_NR	(8)

#define EXYNOS4210_GPIO_Y6_NR	(8)

#define EXYNOS4210_GPIO_X0_NR	(8)

#define EXYNOS4210_GPIO_X1_NR	(8)

#define EXYNOS4210_GPIO_X2_NR	(8)

#define EXYNOS4210_GPIO_X3_NR	(8)

#define EXYNOS4210_GPIO_Z_NR	(7)



enum exynos4210_gpio_xa_start {

	EXYNOS4210_GPIO_A0_START	= 0,

	EXYNOS4210_GPIO_A1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),

	EXYNOS4210_GPIO_B_START		= EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),

	EXYNOS4210_GPIO_C0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),

	EXYNOS4210_GPIO_C1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),

	EXYNOS4210_GPIO_D0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),

	EXYNOS4210_GPIO_D1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),

	EXYNOS4210_GPIO_E0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),

	EXYNOS4210_GPIO_E1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),

	EXYNOS4210_GPIO_E2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),

	EXYNOS4210_GPIO_E3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),

	EXYNOS4210_GPIO_E4_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),

	EXYNOS4210_GPIO_F0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),

	EXYNOS4210_GPIO_F1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),

	EXYNOS4210_GPIO_F2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),

	EXYNOS4210_GPIO_F3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),

};



enum exynos4210_gpio_xb_start {

	EXYNOS4210_GPIO_J0_START	= 0,

	EXYNOS4210_GPIO_J1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),

	EXYNOS4210_GPIO_K0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),

	EXYNOS4210_GPIO_K1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),

	EXYNOS4210_GPIO_K2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),

	EXYNOS4210_GPIO_K3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),

	EXYNOS4210_GPIO_L0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),

	EXYNOS4210_GPIO_L1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),

	EXYNOS4210_GPIO_L2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),

	EXYNOS4210_GPIO_Y0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),

	EXYNOS4210_GPIO_Y1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),

	EXYNOS4210_GPIO_Y2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),

	EXYNOS4210_GPIO_Y3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),

	EXYNOS4210_GPIO_Y4_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),

	EXYNOS4210_GPIO_Y5_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),

	EXYNOS4210_GPIO_Y6_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),

	EXYNOS4210_GPIO_X0_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),

	EXYNOS4210_GPIO_X1_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),

	EXYNOS4210_GPIO_X2_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),

	EXYNOS4210_GPIO_X3_START	= EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),

};



enum exynos4210_gpio_xc_start {

	EXYNOS4210_GPIO_Z_START		= 0,

};



#define	EXYNOS4210_GPIO_A0_IRQ		EXYNOS4210_GPIO_A0_START

#define	EXYNOS4210_GPIO_A1_IRQ		EXYNOS4210_GPIO_A1_START

#define	EXYNOS4210_GPIO_B_IRQ		EXYNOS4210_GPIO_B_START

#define	EXYNOS4210_GPIO_C0_IRQ		EXYNOS4210_GPIO_C0_START

#define	EXYNOS4210_GPIO_C1_IRQ		EXYNOS4210_GPIO_C1_START

#define	EXYNOS4210_GPIO_D0_IRQ		EXYNOS4210_GPIO_D0_START

#define	EXYNOS4210_GPIO_D1_IRQ		EXYNOS4210_GPIO_D1_START

#define	EXYNOS4210_GPIO_E0_IRQ		EXYNOS4210_GPIO_E0_START

#define	EXYNOS4210_GPIO_E1_IRQ		EXYNOS4210_GPIO_E1_START

#define	EXYNOS4210_GPIO_E2_IRQ		EXYNOS4210_GPIO_E2_START

#define	EXYNOS4210_GPIO_E3_IRQ		EXYNOS4210_GPIO_E3_START

#define	EXYNOS4210_GPIO_E4_IRQ		EXYNOS4210_GPIO_E4_START

#define	EXYNOS4210_GPIO_F0_IRQ		EXYNOS4210_GPIO_F0_START

#define	EXYNOS4210_GPIO_F1_IRQ		EXYNOS4210_GPIO_F1_START

#define	EXYNOS4210_GPIO_F2_IRQ		EXYNOS4210_GPIO_F2_START

#define	EXYNOS4210_GPIO_F3_IRQ		EXYNOS4210_GPIO_F3_START

#define	EXYNOS4210_GPIO_J0_IRQ		EXYNOS4210_GPIO_J0_START

#define	EXYNOS4210_GPIO_J1_IRQ		EXYNOS4210_GPIO_J1_START

#define	EXYNOS4210_GPIO_K0_IRQ		EXYNOS4210_GPIO_K0_START

#define	EXYNOS4210_GPIO_K1_IRQ		EXYNOS4210_GPIO_K1_START

#define	EXYNOS4210_GPIO_K2_IRQ		EXYNOS4210_GPIO_K2_START

#define	EXYNOS4210_GPIO_K3_IRQ		EXYNOS4210_GPIO_K3_START

#define	EXYNOS4210_GPIO_L0_IRQ		EXYNOS4210_GPIO_L0_START

#define	EXYNOS4210_GPIO_L1_IRQ		EXYNOS4210_GPIO_L1_START

#define	EXYNOS4210_GPIO_L2_IRQ		EXYNOS4210_GPIO_L2_START

#define	EXYNOS4210_GPIO_Z_IRQ		EXYNOS4210_GPIO_Z_START



#define EXYNOS4210_GPIOA_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)

#define EXYNOS4210_GPIOA_NR_GINT	EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)

#define EXYNOS4210_GPIOB_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)

#define EXYNOS4210_GPIOB_NR_GINT	EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)

#define EXYNOS4210_GPIOC_NR_PINS	EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)



/* External GPIO and wakeup interrupt related definitions */

#define EXYNOS_GPIO_ECON_OFFSET		0x700

#define EXYNOS_GPIO_EMASK_OFFSET	0x900
@@ -165,11 +46,10 @@ enum exynos4210_gpio_xc_start { 
#define EXYNOS_EINT_MAX_PER_BANK	8

#define EXYNOS_EINT_NR_WKUP_EINT



#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id)		\

#define EXYNOS_PIN_BANK_EINTN(pins, reg, id)		\

	{						\

		.pctl_offset	= reg,			\

		.pin_base	= (__gpio##_START),	\

		.nr_pins	= (__gpio##_NR),	\

		.nr_pins	= pins,			\

		.func_width	= 4,			\

		.pud_width	= 2,			\

		.drv_width	= 2,			\
@@ -179,40 +59,50 @@ enum exynos4210_gpio_xc_start { 
		.name		= id			\

	}



#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id)		\

#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs)	\

	{						\

		.pctl_offset	= reg,			\

		.pin_base	= (__gpio##_START),	\

		.nr_pins	= (__gpio##_NR),	\

		.nr_pins	= pins,			\

		.func_width	= 4,			\

		.pud_width	= 2,			\

		.drv_width	= 2,			\

		.conpdn_width	= 2,			\

		.pudpdn_width	= 2,			\

		.eint_type	= EINT_TYPE_GPIO,	\

		.irq_base	= (__gpio##_IRQ),	\

		.eint_offset	= offs,			\

		.name		= id			\

	}



#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs)	\

	{						\

		.pctl_offset	= reg,			\

		.nr_pins	= pins,			\

		.func_width	= 4,			\

		.pud_width	= 2,			\

		.drv_width	= 2,			\

		.eint_type	= EINT_TYPE_WKUP,	\

		.eint_offset	= offs,			\

		.name		= id			\

	}



/**

 * struct exynos_geint_data: gpio eint specific data for irq_chip callbacks.

 * @bank: pin bank from which this gpio interrupt originates.

 * @pin: pin number within the bank.

 * @eint_offset: offset to be added to the con/pend/mask register bank base.

 * struct exynos_weint_data: irq specific data for all the wakeup interrupts

 * generated by the external wakeup interrupt controller.

 * @irq: interrupt number within the domain.

 * @bank: bank responsible for this interrupt

 */

struct exynos_geint_data {

struct exynos_weint_data {

	unsigned int irq;

	struct samsung_pin_bank *bank;

	u32			pin;

	u32			eint_offset;

};



/**

 * struct exynos_weint_data: irq specific data for all the wakeup interrupts

 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts

 * generated by the external wakeup interrupt controller.

 * @domain: irq domain representing the external wakeup interrupts

 * @irq: interrupt number within the domain.

 * @nr_banks: count of banks being part of the mux

 * @banks: array of banks being part of the mux

 */

struct exynos_weint_data {

	struct irq_domain	*domain;

	u32			irq;

struct exynos_muxed_weint_data {

	unsigned int nr_banks;

	struct samsung_pin_bank *banks[];

};