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Commit 66f13762 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: move common function to smu7_smumgr.c 



fiji and polaris can share same setup_pwr_virus
function.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 26f52781

drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h

deleted100644 → 0
+0 −2007

File deleted.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

+1 −42
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ 
#include "gca/gfx_8_0_d.h"

#include "bif/bif_5_0_d.h"

#include "bif/bif_5_0_sh_mask.h"

#include "fiji_pwrvirus.h"

#include "fiji_smc.h"



#define AVFS_EN_MSB                                        1568
@@ -159,46 +158,6 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) 
	return result;

}



static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)

{

	int i;

	uint32_t reg, data;



	for (i = 0; i < size; i++) {

		reg  = pvirus->reg;

		data = pvirus->data;

		if (reg != 0xffffffff)

			cgs_write_register(hwmgr->device, reg, data);

		else

			break;

		pvirus++;

	}

}



static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)

{

	int i;

	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);

	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);

	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);

	for (i = 0; i < section->dfy_size; i++)

		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);

}



static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)

{

	execute_pwr_table(hwmgr, PwrVirusTable_pre, ARRAY_SIZE(PwrVirusTable_pre));

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);

	execute_pwr_table(hwmgr, PwrVirusTable_post, ARRAY_SIZE(PwrVirusTable_post));



	return 0;

}



static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)

{

	int result = 0;
@@ -277,7 +236,7 @@ static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started) 
				" table over to SMU",

				return -EINVAL;);

		smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;

		PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(hwmgr),

		PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),

				"[AVFS][fiji_avfs_event_mgr] Could not setup "

				"Pwr Virus for AVFS ",

				return -EINVAL;);

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

+1 −42
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#include "gca/gfx_8_0_d.h"

#include "bif/bif_5_0_d.h"

#include "bif/bif_5_0_sh_mask.h"

#include "polaris10_pwrvirus.h"

#include "ppatomctrl.h"

#include "cgs_common.h"

#include "polaris10_smc.h"
@@ -60,46 +59,6 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { 
static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {

	0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};



static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)

{

	int i;

	uint32_t reg, data;



	for (i = 0; i < size; i++) {

		reg  = pvirus->reg;

		data = pvirus->data;

		if (reg != 0xffffffff)

			cgs_write_register(hwmgr->device, reg, data);

		else

			break;

		pvirus++;

	}

}



static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)

{

	int i;

	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);

	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);

	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);

	for (i = 0; i < section->dfy_size; i++)

		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);

}



static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)

{

	execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);

	execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));



	return 0;

}



static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)

{

	int result = 0;
@@ -197,7 +156,7 @@ polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT) 
		if (smu_data->avfs.avfs_btc_param > 1) {

			pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");

			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;

			PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(hwmgr),

			PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),

			"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",

			return -EINVAL);

		}

drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

+44 −2
Original line number Diff line number Diff line
@@ -25,12 +25,13 @@ 
#include "pp_debug.h"

#include "smumgr.h"

#include "smu_ucode_xfer_vi.h"

#include "smu/smu_7_1_3_d.h"

#include "smu/smu_7_1_3_sh_mask.h"

#include "ppatomctrl.h"

#include "cgs_common.h"

#include "smu7_ppsmc.h"

#include "smu7_smumgr.h"

#include "smu7_common.h"



#include "polaris10_pwrvirus.h"



#define SMU7_SMC_SIZE 0x20000
@@ -540,6 +541,47 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr) 
	return result;

}



static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)

{

	int i;

	uint32_t reg, data;



	for (i = 0; i < size; i++) {

		reg  = pvirus->reg;

		data = pvirus->data;

		if (reg != 0xffffffff)

			cgs_write_register(hwmgr->device, reg, data);

		else

			break;

		pvirus++;

	}

}



static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)

{

	int i;



	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);

	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);

	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);

	for (i = 0; i < section->dfy_size; i++)

		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);

}



int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)

{

	execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);

	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);

	execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));



	return 0;

}



int smu7_init(struct pp_hwmgr *hwmgr)

{

	struct smu7_smumgr *smu_data;

drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h

+3 −1
Original line number Diff line number Diff line
@@ -88,4 +88,6 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr); 
int smu7_init(struct pp_hwmgr *hwmgr);

int smu7_smu_fini(struct pp_hwmgr *hwmgr);



int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr);



#endif