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Commit 26f52781 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: implement function notify_cac_buffer_info on VI 



Used for smu power logging.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 52afb85e

drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

+28 −0
Original line number Diff line number Diff line
@@ -1871,6 +1871,33 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, 
	}

}



static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,

					uint32_t virtual_addr_low,

					uint32_t virtual_addr_hi,

					uint32_t mc_addr_low,

					uint32_t mc_addr_hi,

					uint32_t size)

{

	smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DramAddrHiVirtual,

					mc_addr_hi);

	smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DramAddrLoVirtual,

					mc_addr_low);

	smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DramAddrHiPhysical,

					virtual_addr_hi);

	smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DramAddrLoPhysical,

					virtual_addr_low);



	smum_send_msg_to_smc_with_parameter(hwmgr,

					PPSMC_MSG_DramBufferSize,

					size);

	return 0;

}





static const struct pp_hwmgr_func cz_hwmgr_funcs = {

	.backend_init = cz_hwmgr_backend_init,

	.backend_fini = cz_hwmgr_backend_fini,
@@ -1901,6 +1928,7 @@ static const struct pp_hwmgr_func cz_hwmgr_funcs = { 
	.dynamic_state_management_enable = cz_enable_dpm_tasks,

	.power_state_set = cz_set_power_state_tasks,

	.dynamic_state_management_disable = cz_disable_dpm_tasks,

	.notify_cac_buffer_info = cz_notify_cac_buffer_info,

};



int cz_init_function_pointers(struct pp_hwmgr *hwmgr)

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+42 −0
Original line number Diff line number Diff line
@@ -4645,6 +4645,47 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 
	return 0;

}



static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,

					uint32_t virtual_addr_low,

					uint32_t virtual_addr_hi,

					uint32_t mc_addr_low,

					uint32_t mc_addr_hi,

					uint32_t size)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);



	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

					data->soft_regs_start +

					smum_get_offsetof(hwmgr,

					SMU_SoftRegisters, DRAM_LOG_ADDR_H),

					mc_addr_hi);



	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

					data->soft_regs_start +

					smum_get_offsetof(hwmgr,

					SMU_SoftRegisters, DRAM_LOG_ADDR_L),

					mc_addr_low);



	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

					data->soft_regs_start +

					smum_get_offsetof(hwmgr,

					SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),

					virtual_addr_hi);



	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

					data->soft_regs_start +

					smum_get_offsetof(hwmgr,

					SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),

					virtual_addr_low);



	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

					data->soft_regs_start +

					smum_get_offsetof(hwmgr,

					SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),

					size);

	return 0;

}



static const struct pp_hwmgr_func smu7_hwmgr_funcs = {

	.backend_init = &smu7_hwmgr_backend_init,

	.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4696,6 +4737,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 
	.avfs_control = smu7_avfs_control,

	.disable_smc_firmware_ctf = smu7_thermal_disable_alert,

	.start_thermal_controller = smu7_start_thermal_controller,

	.notify_cac_buffer_info = smu7_notify_cac_buffer_info,

};



uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

+5 −0
Original line number Diff line number Diff line
@@ -75,6 +75,11 @@ enum SMU_MEMBER { 
	VceBootLevel,

	SamuBootLevel,

	LowSclkInterruptThreshold,

	DRAM_LOG_ADDR_H,

	DRAM_LOG_ADDR_L,

	DRAM_LOG_PHY_ADDR_H,

	DRAM_LOG_PHY_ADDR_L,

	DRAM_LOG_BUFF_SIZE,

};

drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c

+10 −0
Original line number Diff line number Diff line
@@ -2266,6 +2266,16 @@ static uint32_t ci_get_offsetof(uint32_t type, uint32_t member) 
			return offsetof(SMU7_SoftRegisters, PreVBlankGap);

		case VBlankTimeout:

			return offsetof(SMU7_SoftRegisters, VBlankTimeout);

		case DRAM_LOG_ADDR_H:

			return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);

		case DRAM_LOG_ADDR_L:

			return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);

		case DRAM_LOG_PHY_ADDR_H:

			return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);

		case DRAM_LOG_PHY_ADDR_L:

			return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);

		case DRAM_LOG_BUFF_SIZE:

			return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);

		}

	case SMU_Discrete_DpmTable:

		switch (member) {

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c

+10 −0
Original line number Diff line number Diff line
@@ -2199,6 +2199,16 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member) 
			return offsetof(SMU73_SoftRegisters, VBlankTimeout);

		case UcodeLoadStatus:

			return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);

		case DRAM_LOG_ADDR_H:

			return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);

		case DRAM_LOG_ADDR_L:

			return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);

		case DRAM_LOG_PHY_ADDR_H:

			return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);

		case DRAM_LOG_PHY_ADDR_L:

			return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);

		case DRAM_LOG_BUFF_SIZE:

			return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);

		}

	case SMU_Discrete_DpmTable:

		switch (member) {