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Commit 66a6c317 authored by Kumar Gala's avatar Kumar Gala
Browse files

ARM: dts: qcom: Update msm8660 device trees 



* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
  should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller

Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
parent 665c9c03

arch/arm/boot/dts/qcom-msm8660-surf.dts

+10 −0
Original line number Diff line number Diff line
@@ -3,4 +3,14 @@ 
/ {

	model = "Qualcomm MSM8660 SURF";

	compatible = "qcom,msm8660-surf", "qcom,msm8660";



	soc {

		gsbi@19c00000 {

			status = "ok";

			qcom,mode = <GSBI_PROT_I2C_UART>;

			serial@19c40000 {

				status = "ok";

			};

		};

	};

};

arch/arm/boot/dts/qcom-msm8660.dtsi

+68 −47
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
/include/ "skeleton.dtsi"



#include <dt-bindings/clock/qcom,gcc-msm8660.h>

#include <dt-bindings/soc/qcom,gsbi.h>



/ {

	model = "Qualcomm MSM8660";
@@ -12,16 +13,18 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,scorpion";

		enable-method = "qcom,gcc-msm8660";



		cpu@0 {

			compatible = "qcom,scorpion";

			enable-method = "qcom,gcc-msm8660";

			device_type = "cpu";

			reg = <0>;

			next-level-cache = <&L2>;

		};



		cpu@1 {

			compatible = "qcom,scorpion";

			enable-method = "qcom,gcc-msm8660";

			device_type = "cpu";

			reg = <1>;

			next-level-cache = <&L2>;
@@ -33,6 +36,12 @@ 
		};

	};



	soc: soc {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		compatible = "simple-bus";



		intc: interrupt-controller@2080000 {

			compatible = "qcom,msm-8660-qgic";

			interrupt-controller;
@@ -70,6 +79,15 @@ 
			reg = <0x900000 0x4000>;

		};



		gsbi12: gsbi@19c00000 {

			compatible = "qcom,gsbi-v1.0.0";

			reg = <0x19c00000 0x100>;

			clocks = <&gcc GSBI12_H_CLK>;

			clock-names = "iface";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			serial@19c40000 {

				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x19c40000 0x1000>,
@@ -77,6 +95,8 @@ 
				interrupts = <0 195 0x0>;

				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";

			};

		};



		qcom,ssbi@500000 {
@@ -85,3 +105,4 @@ 
			qcom,controller-type = "pmic-arbiter";

		};

	};

};