Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 665c9c03 authored by Kumar Gala's avatar Kumar Gala
Browse files

ARM: dts: qcom: Update msm8960 device trees 



* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
  should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
  binding spec
* Add GSBI node and configuration of GSBI controller

Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
parent ba08220a

arch/arm/boot/dts/qcom-msm8960-cdp.dts

+10 −0
Original line number Diff line number Diff line
@@ -3,4 +3,14 @@ 
/ {

	model = "Qualcomm MSM8960 CDP";

	compatible = "qcom,msm8960-cdp", "qcom,msm8960";



	soc {

		gsbi@16400000 {

			status = "ok";

			qcom,mode = <GSBI_PROT_I2C_UART>;

			serial@16440000 {

				status = "ok";

			};

		};

	};

};

arch/arm/boot/dts/qcom-msm8960.dtsi

+98 −78
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
/include/ "skeleton.dtsi"



#include <dt-bindings/clock/qcom,gcc-msm8960.h>

#include <dt-bindings/soc/qcom,gsbi.h>



/ {

	model = "Qualcomm MSM8960";
@@ -13,10 +14,10 @@ 
		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <1 14 0x304>;

		compatible = "qcom,krait";

		enable-method = "qcom,kpss-acc-v1";



		cpu@0 {

			compatible = "qcom,krait";

			enable-method = "qcom,kpss-acc-v1";

			device_type = "cpu";

			reg = <0>;

			next-level-cache = <&L2>;
@@ -25,6 +26,8 @@ 
		};



		cpu@1 {

			compatible = "qcom,krait";

			enable-method = "qcom,kpss-acc-v1";

			device_type = "cpu";

			reg = <1>;

			next-level-cache = <&L2>;
@@ -35,7 +38,6 @@ 
		L2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			interrupts = <0 2 0x4>;

		};

	};
@@ -45,6 +47,12 @@ 
		qcom,no-pc-write;

	};



	soc: soc {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		compatible = "simple-bus";



		intc: interrupt-controller@2000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;
@@ -111,6 +119,15 @@ 
			regulator;

		};



		gsbi5: gsbi@16400000 {

			compatible = "qcom,gsbi-v1.0.0";

			reg = <0x16400000 0x100>;

			clocks = <&gcc GSBI5_H_CLK>;

			clock-names = "iface";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			serial@16440000 {

				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x16440000 0x1000>,
@@ -118,6 +135,8 @@ 
				interrupts = <0 154 0x0>;

				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";

			};

		};



		qcom,ssbi@500000 {
@@ -133,3 +152,4 @@ 
			clock-names = "core";

		};

	};

};