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Commit 63a4dec2 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Daniel Vetter
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drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGating 



Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarAlex Dai <yu.dai@intel.com>
[danvet: Fix continuation alignment.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e3429cd2

drivers/gpu/drm/i915/intel_pm.c

+7 −1
Original line number Diff line number Diff line
@@ -4854,6 +4854,12 @@ static void gen9_enable_rc6(struct drm_device *dev) 
	I915_WRITE(GEN6_RC_CONTROL, 0);



	/* 2b: Program RC6 thresholds.*/



	/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */

	if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&

				 (INTEL_REVID(dev) <= SKL_REVID_E0)))

		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);

	else

		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);

	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */

	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */