Merge "dt-bindings: clock: remove mdss dp crypto clocks" (62de338c) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm64/boot/dts/qcom/kona-sde.dtsi

+1 −2

Original line number	Diff line number	Diff line
		@@ -345,7 +345,6 @@
		<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
		<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
		<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
		<&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
		<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
		<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
		<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
		@@ -354,7 +353,7 @@
		<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
		clock-names = "core_aux_clk", "core_usb_ref_clk_src",
		"core_usb_pipe_clk", "link_clk", "link_iface_clk",
		"crypto_clk", "pixel_clk_rcg", "pixel_parent",
		"pixel_clk_rcg", "pixel_parent",
		"pixel1_clk_rcg", "pixel1_parent",
		"strm0_pixel_clk", "strm1_pixel_clk";

drivers/clk/qcom/debugcc-kona.c

+0 −6

Original line number	Diff line number	Diff line
		@@ -93,8 +93,6 @@ static const char *const debug_mux_parent_names[] = {
		"disp_cc_mdss_byte1_intf_clk",
		"disp_cc_mdss_dp_aux1_clk",
		"disp_cc_mdss_dp_aux_clk",
		"disp_cc_mdss_dp_crypto1_clk",
		"disp_cc_mdss_dp_crypto_clk",
		"disp_cc_mdss_dp_link1_clk",
		"disp_cc_mdss_dp_link1_intf_clk",
		"disp_cc_mdss_dp_link_clk",
		@@ -431,10 +429,6 @@ static struct clk_debug_mux gcc_debug_mux = {
		0x25, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },
		{ "disp_cc_mdss_dp_aux_clk", 0x56, 2, DISP_CC,
		0x20, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },
		{ "disp_cc_mdss_dp_crypto1_clk", 0x56, 2, DISP_CC,
		0x24, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },
		{ "disp_cc_mdss_dp_crypto_clk", 0x56, 2, DISP_CC,
		0x1D, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },
		{ "disp_cc_mdss_dp_link1_clk", 0x56, 2, DISP_CC,
		0x22, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C },
		{ "disp_cc_mdss_dp_link1_intf_clk", 0x56, 2, DISP_CC,

drivers/clk/qcom/dispcc-kona.c

+0 −95

Original line number	Diff line number	Diff line
		@@ -422,60 +422,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
		},
		};

		static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto1_clk_src[] = {
		F( 108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
		F( 180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
		F( 360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
		F( 540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
		{ }
		};

		static struct clk_rcg2 disp_cc_mdss_dp_crypto1_clk_src = {
		.cmd_rcgr = 0x2228,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_0,
		.freq_tbl = ftbl_disp_cc_mdss_dp_crypto1_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_dp_crypto1_clk_src",
		.parent_names = disp_cc_parent_names_0,
		.num_parents = 8,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_mm,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 12800,
		[VDD_LOWER] = 108000,
		[VDD_LOW] = 180000,
		[VDD_LOW_L1] = 360000,
		[VDD_NOMINAL] = 540000},
		},
		};

		static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
		.cmd_rcgr = 0x2194,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_0,
		.freq_tbl = ftbl_disp_cc_mdss_dp_crypto1_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_dp_crypto_clk_src",
		.parent_names = disp_cc_parent_names_0,
		.num_parents = 8,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_mm,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 12800,
		[VDD_LOWER] = 108000,
		[VDD_LOW] = 180000,
		[VDD_LOW_L1] = 360000,
		[VDD_NOMINAL] = 540000},
		},
		};

		static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
		F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
		F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
		@@ -997,42 +943,6 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = {
		},
		};

		static struct clk_branch disp_cc_mdss_dp_crypto1_clk = {
		.halt_reg = 0x2064,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2064,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_dp_crypto1_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_dp_crypto1_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
		.halt_reg = 0x2048,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2048,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_dp_crypto_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_dp_crypto_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_dp_link1_clk = {
		.halt_reg = 0x205c,
		.halt_check = BRANCH_HALT,
		@@ -1493,11 +1403,6 @@ static struct clk_regmap *disp_cc_kona_clocks[] = {
		[DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
		[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
		[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
		[DISP_CC_MDSS_DP_CRYPTO1_CLK] = &disp_cc_mdss_dp_crypto1_clk.clkr,
		[DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC] =
		&disp_cc_mdss_dp_crypto1_clk_src.clkr,
		[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
		[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
		[DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
		[DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
		[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] =

include/dt-bindings/clock/qcom,dispcc-kona.h

+47 −51

Original line number	Diff line number	Diff line
		@@ -21,57 +21,53 @@
		#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
		#define DISP_CC_MDSS_DP_AUX_CLK 12
		#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
		#define DISP_CC_MDSS_DP_CRYPTO1_CLK 14
		#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC 15
		#define DISP_CC_MDSS_DP_CRYPTO_CLK 16
		#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 17
		#define DISP_CC_MDSS_DP_LINK1_CLK 18
		#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 19
		#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 20
		#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 21
		#define DISP_CC_MDSS_DP_LINK_CLK 22
		#define DISP_CC_MDSS_DP_LINK_CLK_SRC 23
		#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 24
		#define DISP_CC_MDSS_DP_LINK_INTF_CLK 25
		#define DISP_CC_MDSS_DP_PIXEL1_CLK 26
		#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 27
		#define DISP_CC_MDSS_DP_PIXEL2_CLK 28
		#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 29
		#define DISP_CC_MDSS_DP_PIXEL_CLK 30
		#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 31
		#define DISP_CC_MDSS_EDP_AUX_CLK 32
		#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 33
		#define DISP_CC_MDSS_EDP_GTC_CLK 34
		#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 35
		#define DISP_CC_MDSS_EDP_LINK_CLK 36
		#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 37
		#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 38
		#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 39
		#define DISP_CC_MDSS_EDP_PIXEL_CLK 40
		#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 41
		#define DISP_CC_MDSS_ESC0_CLK 42
		#define DISP_CC_MDSS_ESC0_CLK_SRC 43
		#define DISP_CC_MDSS_ESC1_CLK 44
		#define DISP_CC_MDSS_ESC1_CLK_SRC 45
		#define DISP_CC_MDSS_MDP_CLK 46
		#define DISP_CC_MDSS_MDP_CLK_SRC 47
		#define DISP_CC_MDSS_MDP_LUT_CLK 48
		#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 49
		#define DISP_CC_MDSS_PCLK0_CLK 50
		#define DISP_CC_MDSS_PCLK0_CLK_SRC 51
		#define DISP_CC_MDSS_PCLK1_CLK 52
		#define DISP_CC_MDSS_PCLK1_CLK_SRC 53
		#define DISP_CC_MDSS_ROT_CLK 54
		#define DISP_CC_MDSS_ROT_CLK_SRC 55
		#define DISP_CC_MDSS_RSCC_AHB_CLK 56
		#define DISP_CC_MDSS_RSCC_VSYNC_CLK 57
		#define DISP_CC_MDSS_VSYNC_CLK 58
		#define DISP_CC_MDSS_VSYNC_CLK_SRC 59
		#define DISP_CC_PLL0 60
		#define DISP_CC_PLL1 61
		#define DISP_CC_SLEEP_CLK 62
		#define DISP_CC_SLEEP_CLK_SRC 63
		#define DISP_CC_XO_CLK 64
		#define DISP_CC_MDSS_DP_LINK1_CLK 14
		#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
		#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
		#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
		#define DISP_CC_MDSS_DP_LINK_CLK 18
		#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
		#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
		#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
		#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
		#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
		#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
		#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
		#define DISP_CC_MDSS_DP_PIXEL_CLK 26
		#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
		#define DISP_CC_MDSS_EDP_AUX_CLK 28
		#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 29
		#define DISP_CC_MDSS_EDP_GTC_CLK 30
		#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 31
		#define DISP_CC_MDSS_EDP_LINK_CLK 32
		#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 33
		#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 34
		#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 35
		#define DISP_CC_MDSS_EDP_PIXEL_CLK 36
		#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 37
		#define DISP_CC_MDSS_ESC0_CLK 38
		#define DISP_CC_MDSS_ESC0_CLK_SRC 39
		#define DISP_CC_MDSS_ESC1_CLK 40
		#define DISP_CC_MDSS_ESC1_CLK_SRC 41
		#define DISP_CC_MDSS_MDP_CLK 42
		#define DISP_CC_MDSS_MDP_CLK_SRC 43
		#define DISP_CC_MDSS_MDP_LUT_CLK 44
		#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 45
		#define DISP_CC_MDSS_PCLK0_CLK 46
		#define DISP_CC_MDSS_PCLK0_CLK_SRC 47
		#define DISP_CC_MDSS_PCLK1_CLK 48
		#define DISP_CC_MDSS_PCLK1_CLK_SRC 49
		#define DISP_CC_MDSS_ROT_CLK 50
		#define DISP_CC_MDSS_ROT_CLK_SRC 51
		#define DISP_CC_MDSS_RSCC_AHB_CLK 52
		#define DISP_CC_MDSS_RSCC_VSYNC_CLK 53
		#define DISP_CC_MDSS_VSYNC_CLK 54
		#define DISP_CC_MDSS_VSYNC_CLK_SRC 55
		#define DISP_CC_PLL0 56
		#define DISP_CC_PLL1 57
		#define DISP_CC_SLEEP_CLK 58
		#define DISP_CC_SLEEP_CLK_SRC 59
		#define DISP_CC_XO_CLK 60

		/* DISP_CC resets */
		#define DISP_CC_MDSS_CORE_BCR 0