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Commit 748deffb authored by David Dai's avatar David Dai
Browse files

dt-bindings: clock: remove mdss dp crypto clocks 



Remove the IDs for mdss dp crypto clocks that are not
under software control.

Change-Id: I279727eaf89dcbbba55d92ebff4d55d096232dee
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent 34b71469

include/dt-bindings/clock/qcom,dispcc-kona.h

+47 −51
Original line number Diff line number Diff line
@@ -21,57 +21,53 @@ 
#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				11

#define DISP_CC_MDSS_DP_AUX_CLK					12

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				15

#define DISP_CC_MDSS_DP_CRYPTO_CLK				16

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_CLK				18

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				19

#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC			20

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				21

#define DISP_CC_MDSS_DP_LINK_CLK				22

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				23

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			24

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				25

#define DISP_CC_MDSS_DP_PIXEL1_CLK				26

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				27

#define DISP_CC_MDSS_DP_PIXEL2_CLK				28

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				29

#define DISP_CC_MDSS_DP_PIXEL_CLK				30

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				31

#define DISP_CC_MDSS_EDP_AUX_CLK				32

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				33

#define DISP_CC_MDSS_EDP_GTC_CLK				34

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				35

#define DISP_CC_MDSS_EDP_LINK_CLK				36

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				37

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC			38

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				39

#define DISP_CC_MDSS_EDP_PIXEL_CLK				40

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				41

#define DISP_CC_MDSS_ESC0_CLK					42

#define DISP_CC_MDSS_ESC0_CLK_SRC				43

#define DISP_CC_MDSS_ESC1_CLK					44

#define DISP_CC_MDSS_ESC1_CLK_SRC				45

#define DISP_CC_MDSS_MDP_CLK					46

#define DISP_CC_MDSS_MDP_CLK_SRC				47

#define DISP_CC_MDSS_MDP_LUT_CLK				48

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				49

#define DISP_CC_MDSS_PCLK0_CLK					50

#define DISP_CC_MDSS_PCLK0_CLK_SRC				51

#define DISP_CC_MDSS_PCLK1_CLK					52

#define DISP_CC_MDSS_PCLK1_CLK_SRC				53

#define DISP_CC_MDSS_ROT_CLK					54

#define DISP_CC_MDSS_ROT_CLK_SRC				55

#define DISP_CC_MDSS_RSCC_AHB_CLK				56

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				57

#define DISP_CC_MDSS_VSYNC_CLK					58

#define DISP_CC_MDSS_VSYNC_CLK_SRC				59

#define DISP_CC_PLL0						60

#define DISP_CC_PLL1						61

#define DISP_CC_SLEEP_CLK					62

#define DISP_CC_SLEEP_CLK_SRC					63

#define DISP_CC_XO_CLK						64

#define DISP_CC_MDSS_DP_LINK1_CLK				14

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				15

#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC			16

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				17

#define DISP_CC_MDSS_DP_LINK_CLK				18

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				19

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			20

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				21

#define DISP_CC_MDSS_DP_PIXEL1_CLK				22

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				23

#define DISP_CC_MDSS_DP_PIXEL2_CLK				24

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				25

#define DISP_CC_MDSS_DP_PIXEL_CLK				26

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				27

#define DISP_CC_MDSS_EDP_AUX_CLK				28

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				29

#define DISP_CC_MDSS_EDP_GTC_CLK				30

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				31

#define DISP_CC_MDSS_EDP_LINK_CLK				32

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				33

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC			34

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				35

#define DISP_CC_MDSS_EDP_PIXEL_CLK				36

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				37

#define DISP_CC_MDSS_ESC0_CLK					38

#define DISP_CC_MDSS_ESC0_CLK_SRC				39

#define DISP_CC_MDSS_ESC1_CLK					40

#define DISP_CC_MDSS_ESC1_CLK_SRC				41

#define DISP_CC_MDSS_MDP_CLK					42

#define DISP_CC_MDSS_MDP_CLK_SRC				43

#define DISP_CC_MDSS_MDP_LUT_CLK				44

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				45

#define DISP_CC_MDSS_PCLK0_CLK					46

#define DISP_CC_MDSS_PCLK0_CLK_SRC				47

#define DISP_CC_MDSS_PCLK1_CLK					48

#define DISP_CC_MDSS_PCLK1_CLK_SRC				49

#define DISP_CC_MDSS_ROT_CLK					50

#define DISP_CC_MDSS_ROT_CLK_SRC				51

#define DISP_CC_MDSS_RSCC_AHB_CLK				52

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				53

#define DISP_CC_MDSS_VSYNC_CLK					54

#define DISP_CC_MDSS_VSYNC_CLK_SRC				55

#define DISP_CC_PLL0						56

#define DISP_CC_PLL1						57

#define DISP_CC_SLEEP_CLK					58

#define DISP_CC_SLEEP_CLK_SRC					59

#define DISP_CC_XO_CLK						60



/* DISP_CC resets */

#define DISP_CC_MDSS_CORE_BCR					0