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Commit 62a3a126 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes 

As promised bdw fixes come separate for now. Just a few minior things.

* 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwell
  drm/i915/bdw: Limit GTT to 2GB
  drm/i915/bdw: Add comment about gen8 HWS PGA
  drm/i915/bdw: Free correct number of ppgtt pages
  drm/i915/bdw: Do gen6 style reset for gen8
  drm/i915/bdw: GEN8 backlight support
  drm/i915/bdw: Add BDW to ULT macro
parents 9538e100 596cc11e

drivers/gpu/drm/i915/i915_drv.h

+6 −1
Original line number Diff line number Diff line
@@ -1755,8 +1755,13 @@ struct drm_i915_file_private { 
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \

				 ((dev)->pdev->device & 0xFF00) == 0x0C00)

#define IS_ULT(dev)		(IS_HASWELL(dev) && \

#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \

				 (((dev)->pdev->device & 0xf) == 0x2  || \

				 ((dev)->pdev->device & 0xf) == 0x6 || \

				 ((dev)->pdev->device & 0xf) == 0xe))

#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \

				 ((dev)->pdev->device & 0xFF00) == 0x0A00)

#define IS_ULT(dev)		(IS_HSW_ULT(dev) || IS_BDW_ULT(dev))

#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \

				 ((dev)->pdev->device & 0x00F0) == 0x0020)

#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)

drivers/gpu/drm/i915/i915_gem_gtt.c

+7 −2
Original line number Diff line number Diff line
@@ -337,8 +337,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) 
		kfree(ppgtt->gen8_pt_dma_addr[i]);

	}



	__free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT);

	__free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT);

	__free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));

	__free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));

}



/**
@@ -1241,6 +1241,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) 
	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;

	if (bdw_gmch_ctl)

		bdw_gmch_ctl = 1 << bdw_gmch_ctl;

	if (bdw_gmch_ctl > 4) {

		WARN_ON(!i915_preliminary_hw_support);

		return 4<<20;

	}



	return bdw_gmch_ctl << 20;

}

drivers/gpu/drm/i915/intel_panel.c

+23 −3
Original line number Diff line number Diff line
@@ -451,7 +451,9 @@ static u32 intel_panel_get_backlight(struct drm_device *dev, 


	spin_lock_irqsave(&dev_priv->backlight.lock, flags);



	if (HAS_PCH_SPLIT(dev)) {

	if (IS_BROADWELL(dev)) {

		val = I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;

	} else if (HAS_PCH_SPLIT(dev)) {

		val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

	} else {

		if (IS_VALLEYVIEW(dev))
@@ -479,6 +481,13 @@ static u32 intel_panel_get_backlight(struct drm_device *dev, 
	return val;

}



static void intel_bdw_panel_set_backlight(struct drm_device *dev, u32 level)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;

	I915_WRITE(BLC_PWM_PCH_CTL2, val | level);

}



static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -496,7 +505,9 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev, 
	DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);

	level = intel_panel_compute_brightness(dev, pipe, level);



	if (HAS_PCH_SPLIT(dev))

	if (IS_BROADWELL(dev))

		return intel_bdw_panel_set_backlight(dev, level);

	else if (HAS_PCH_SPLIT(dev))

		return intel_pch_panel_set_backlight(dev, level);



	if (is_backlight_combination_mode(dev)) {
@@ -666,7 +677,16 @@ void intel_panel_enable_backlight(struct intel_connector *connector) 
		POSTING_READ(reg);

		I915_WRITE(reg, tmp | BLM_PWM_ENABLE);



		if (HAS_PCH_SPLIT(dev) &&

		if (IS_BROADWELL(dev)) {

			/*

			 * Broadwell requires PCH override to drive the PCH

			 * backlight pin. The above will configure the CPU

			 * backlight pin, which we don't plan to use.

			 */

			tmp = I915_READ(BLC_PWM_PCH_CTL1);

			tmp |= BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE;

			I915_WRITE(BLC_PWM_PCH_CTL1, tmp);

		} else if (HAS_PCH_SPLIT(dev) &&

		    !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {

			tmp = I915_READ(BLC_PWM_PCH_CTL1);

			tmp |= BLM_PCH_PWM_ENABLE;

drivers/gpu/drm/i915/intel_pm.c

+17 −1
Original line number Diff line number Diff line
@@ -5685,6 +5685,7 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	bool is_enabled, enable_requested;

	unsigned long irqflags;

	uint32_t tmp;



	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
@@ -5702,9 +5703,24 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) 
				      HSW_PWR_WELL_STATE_ENABLED), 20))

				DRM_ERROR("Timeout enabling power well\n");

		}



		if (IS_BROADWELL(dev)) {

			spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

			I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),

				   dev_priv->de_irq_mask[PIPE_B]);

			I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),

				   ~dev_priv->de_irq_mask[PIPE_B] |

				   GEN8_PIPE_VBLANK);

			I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),

				   dev_priv->de_irq_mask[PIPE_C]);

			I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),

				   ~dev_priv->de_irq_mask[PIPE_C] |

				   GEN8_PIPE_VBLANK);

			POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));

			spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		}

	} else {

		if (enable_requested) {

			unsigned long irqflags;

			enum pipe p;



			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);

drivers/gpu/drm/i915/intel_ringbuffer.c

+1 −0
Original line number Diff line number Diff line
@@ -965,6 +965,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) 
	} else if (IS_GEN6(ring->dev)) {

		mmio = RING_HWS_PGA_GEN6(ring->mmio_base);

	} else {

		/* XXX: gen8 returns to sanity */

		mmio = RING_HWS_PGA(ring->mmio_base);

	}