Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 596cc11e authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwell 



The pipe B and pipe C interrupt mask and enable registers are now part
of the pipe, so disabling the pipe power wells will lost the contests of
the registers.

Art totally debugged this one!

v2: Use the irq_lock to clarify code, and prevent future bugs (Daniel)

Cc: Art Runyan <arthur.j.runyan@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
[danvet: Make sparse happy.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3a2ffb65

drivers/gpu/drm/i915/intel_pm.c

+17 −1
Original line number Original line Diff line number Diff line
@@ -5684,6 +5684,7 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) 
{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	bool is_enabled, enable_requested;

	bool is_enabled, enable_requested;

	unsigned long irqflags;

	uint32_t tmp;

	uint32_t tmp;





	tmp = I915_READ(HSW_PWR_WELL_DRIVER);

	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
@@ -5701,9 +5702,24 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) 
				      HSW_PWR_WELL_STATE_ENABLED), 20))

				      HSW_PWR_WELL_STATE_ENABLED), 20))

				DRM_ERROR("Timeout enabling power well\n");

				DRM_ERROR("Timeout enabling power well\n");

		}

		}



		if (IS_BROADWELL(dev)) {

			spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

			I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),

				   dev_priv->de_irq_mask[PIPE_B]);

			I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),

				   ~dev_priv->de_irq_mask[PIPE_B] |

				   GEN8_PIPE_VBLANK);

			I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),

				   dev_priv->de_irq_mask[PIPE_C]);

			I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),

				   ~dev_priv->de_irq_mask[PIPE_C] |

				   GEN8_PIPE_VBLANK);

			POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));

			spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		}

	} else {

	} else {

		if (enable_requested) {

		if (enable_requested) {

			unsigned long irqflags;

			enum pipe p;

			enum pipe p;





			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);

			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);