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Commit 6222709d authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915/skl: Make the Misc I/O power well part of the PLLS domain 



The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
the PLLS power domain to ensure those two power wells are up.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 57520bc5

drivers/gpu/drm/i915/intel_runtime_pm.c

+1 −0
Original line number Diff line number Diff line
@@ -315,6 +315,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, 
	BIT(POWER_DOMAIN_INIT))

#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (		\

	SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |		\

	BIT(POWER_DOMAIN_PLLS) |			\

	BIT(POWER_DOMAIN_INIT))

#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (		\

	(POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |	\